c0959b4426
Replace the dummy C implementation of SpeculationBarrier() with implementations consisting of the recommended DSB SY + ISB sequence, as recommended by ARM in the whitepaper "Cache Speculation Side-channels" version 2.4, dated October 2018. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
40 lines
1.0 KiB
NASM
40 lines
1.0 KiB
NASM
;------------------------------------------------------------------------------
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;
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; SpeculationBarrier() for AArch64
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;
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; Copyright (c) 2019, Linaro Ltd. All rights reserved.
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;
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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EXPORT SpeculationBarrier
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AREA MemoryBarriers, CODE, READONLY
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;/**
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; Uses as a barrier to stop speculative execution.
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;
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; Ensures that no later instruction will execute speculatively, until all prior
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; instructions have completed.
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;
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;**/
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;VOID
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;EFIAPI
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;SpeculationBarrier (
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; VOID
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; );
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;
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SpeculationBarrier
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dsb
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isb
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bx lr
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END
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