69da506c92
RegisterCpuInterruptHandler did not allow setting exception handlers for anything beyond the timer IRQ. Beyond that, it didn't meet the spec around handling of inputs. RiscVSupervisorModeTrapHandler now will invoke set handlers for both exceptions and interrupts. Two arrays of handlers are maintained - one for exceptions and one for interrupts. For unhandled traps, RiscVSupervisorModeTrapHandler dumps state using the now implemented DumpCpuContext. For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped PC address (SEPC), just like on AArch64 (ELR). This is necessary for X86EmulatorPkg to work as it allows a trap handler to return execution to a different place. Add SSTATUS/STVAL as well, at least for debugging purposes. There is no value in hiding this. Fix nested exception handling. Handler code should not be saving SIE (the value is saved in SSTATUS.SPIE) or directly restored (that's done by SRET). Save and restore the entire SSTATUS and STVAL, too. Cc: Daniel Schaefer <git@danielschaefer.me> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
105 lines
3.8 KiB
ArmAsm
105 lines
3.8 KiB
ArmAsm
/** @file
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RISC-V Processor supervisor mode trap handler
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Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include "CpuExceptionHandlerLib.h"
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.align 3
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.section .entry, "ax", %progbits
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.globl SupervisorModeTrap
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SupervisorModeTrap:
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addi sp, sp, -SMODE_TRAP_REGS_SIZE
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/* Save all general regisers except SP */
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sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
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csrr t0, CSR_SSTATUS
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sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
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csrr t0, CSR_SEPC
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sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
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csrr t0, CSR_STVAL
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sd t0, SMODE_TRAP_REGS_OFFSET(stval)(sp)
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ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
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sd zero, SMODE_TRAP_REGS_OFFSET(zero)(sp)
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sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
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sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
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sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
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sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
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sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
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sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
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sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
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sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
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sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
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sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
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sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
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sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
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sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
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sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
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sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
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sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
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sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
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sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
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sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
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sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
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sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
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sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
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sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
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sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
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sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
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sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
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sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
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sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
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sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
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/* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
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mv a0, sp
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call RiscVSupervisorModeTrapHandler
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/* Restore all general regisers except SP */
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ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
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ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
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ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
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ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
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ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
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ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
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ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
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ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
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ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
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ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
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ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
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ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
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ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
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ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
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ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
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ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
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ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
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ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
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ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
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ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
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ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
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ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
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ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
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ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
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ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
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ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
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ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
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ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
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ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
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ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
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csrw CSR_SEPC, t0
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ld t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
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csrw CSR_SSTATUS, t0
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ld t0, SMODE_TRAP_REGS_OFFSET(stval)(sp)
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csrw CSR_STVAL, t0
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ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
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addi sp, sp, SMODE_TRAP_REGS_SIZE
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sret
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