4d4b81697c
PciEnumerationComplete might be signaled to FSP in Coreboot. So FSP wrapper driver don't need send it again. Add a PCD to control if a FSP API could be skipped from FspWrapperNotifyDxe driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
98 lines
4.7 KiB
Plaintext
98 lines
4.7 KiB
Plaintext
## @file
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# Provides drivers and definitions to support fsp in EDKII bios.
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#
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# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials are licensed and made available under
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# the terms and conditions of the BSD License that accompanies this distribution.
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# The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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##
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[Defines]
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DEC_SPECIFICATION = 0x00010005
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PACKAGE_NAME = IntelFsp2WrapperPkg
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PACKAGE_GUID = FAFE06D4-7245-42D7-9FD2-E5D5E36AB0A0
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PACKAGE_VERSION = 0.1
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[Includes]
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Include
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[LibraryClasses]
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## @libraryclass Provide FSP API related function.
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FspWrapperApiLib|Include/Library/FspWrapperApiLib.h
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FspWrapperApiTestLib|Include/Library/FspWrapperApiTestLib.h
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## @libraryclass Provide FSP hob process related function.
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FspWrapperHobProcessLib|Include/Library/FspWrapperHobProcessLib.h
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## @libraryclass Provide FSP platform related function.
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FspWrapperPlatformLib|Include/Library/FspWrapperPlatformLib.h
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[Guids]
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#
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# GUID defined in package
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#
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gIntelFsp2WrapperTokenSpaceGuid = { 0xa34cf082, 0xf50, 0x4f0d, { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }
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gFspApiPerformanceGuid = { 0xc9122295, 0x56ed, 0x4d4e, { 0x06, 0xa6, 0x50, 0x8d, 0x89, 0x4d, 0x3e, 0x40 } }
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gFspHobGuid = { 0x6d86fb36, 0xba90, 0x472c, { 0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a } }
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[Ppis]
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gFspSiliconInitDonePpiGuid = { 0x4eb6e09c, 0xd256, 0x4e1e, { 0xb5, 0x0a, 0x87, 0x4b, 0xd2, 0x84, 0xb3, 0xde } }
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gTopOfTemporaryRamPpiGuid = { 0x2f3962b2, 0x57c5, 0x44ec, { 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b } }
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[Protocols]
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gAddPerfRecordProtocolGuid = { 0xc4a58d6d, 0x3677, 0x49cb, { 0xa0, 0x0a, 0x94, 0x70, 0x76, 0x5f, 0xb5, 0x5e } }
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################################################################################
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#
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# PCD Declarations section - list of all PCDs Declared by this Package
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# Only this package should be providing the
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# declaration, other packages should not.
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#
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################################################################################
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[PcdsFixedAtBuild, PcdsPatchableInModule]
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## Provides the memory mapped base address of the BIOS CodeCache Flash Device.
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gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001
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## Provides the size of the BIOS Flash Device.
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gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002
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## Indicates the base address of the first Microcode Patch in the Microcode Region
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gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005
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gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006
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## Indicates the offset of the Cpu Microcode.
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gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007
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## Indicate the PEI memory size platform want to report
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gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004
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## Indicate the PEI memory size platform want to report
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gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005
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## This is the base address of FSP-T/M/S
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gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00000301
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## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>
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# If a bit is set, that means this FSP API is skipped.<BR>
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# If a bit is clear, that means this FSP API is NOT skipped.<BR>
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# NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.<BR>
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# BIT[15:0] is for function:<BR>
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# BIT0 - Skip TempRamInit<BR>
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# BIT1 - Skip MemoryInit<BR>
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# BIT2 - Skip TempRamExit<BR>
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# BIT3 - Skip SiliconInit<BR>
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# BIT4 - Skip NotifyPhase<BR>
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# BIT[32:16] is for sub-function:<BR>
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# BIT16 - Skip NotifyPhase (AfterPciEnumeration)<BR>
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# BIT17 - Skip NotifyPhase (ReadyToBoot)<BR>
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# BIT18 - Skip NotifyPhase (EndOfFirmware)<BR>
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# Any undefined BITs are reserved for future use.<BR>
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# @Prompt Skip FSP API from FSP wrapper.
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gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009
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[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001
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