3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
66 lines
2.0 KiB
Plaintext
66 lines
2.0 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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;
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; This program and the accompanying materials are licensed and made available under
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; the terms and conditions of the BSD License that accompanies this distribution.
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; The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;* *;
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;* *;
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;**************************************************************************/
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// LPC Bridge - Device 31, Function 0
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// Define the needed LPC registers used by ASL.
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scope(\_SB)
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{
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OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C)
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Field(ILBR, AnyAcc, NoLock, Preserve)
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{
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Offset(0x08), // 0x08
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PARC, 8,
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PBRC, 8,
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PCRC, 8,
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PDRC, 8,
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PERC, 8,
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PFRC, 8,
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PGRC, 8,
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PHRC, 8,
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Offset(0x88), // 0x88
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, 3,
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UI3E, 1,
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UI4E, 1
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}
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Include ("98_LINK.ASL")
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}
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OperationRegion(LPC0, PCI_Config, 0x00, 0xC0)
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Field(LPC0, AnyAcc, NoLock, Preserve)
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{
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Offset(0x08), // 0x08
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SRID, 8, // Revision ID
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Offset(0x080), // 0x80
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C1EN, 1, // COM1 Enable
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, 31
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}
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Include ("LPC_DEV.ASL")
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