b303605e1b
Changes for V4 ============== 1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode from QuarkPlatformPkg commit to QuarkSocPkg commit 2) Fix incorrect license header in PlatformSecLibModStrs.uni Changes for V3 ============== 1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc This is required because QuarkMin.dsc uses the emulated variable driver that does not preserve any non-volatile UEFI variables across reset. If the condition is met where the memory type information variable needs to be updated, then the system will reset every time the UEFI Shell is run. By setting this PCD to FALSE, then reset action is disabled. 2) Move one binary file to QuarkSocBinPkg 3) Change RMU.bin FILE statements to INF statement in DSC FD region to be compatible with PACKAGES_PATH search for QuarkSocBinPkg Changes for V2 ============== 1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg 2) Configure PcdPciSerialParameters for PCI serial driver for Quark 3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM 4) Convert all UNI files to utf-8 5) Replace tabs with spaces and remove trailing spaces 6) Add License.txt Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Acked-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
134 lines
4.8 KiB
Plaintext
134 lines
4.8 KiB
Plaintext
/** @file
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PCI express expansion ports
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef PcieExpansionPrt_asi
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#define PcieExpansionPrt_asi
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Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0]
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{
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Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0
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Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
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OperationRegion (PES0,PCI_Config,0x40,0xA0)
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Field (PES0, AnyAcc, NoLock, Preserve)
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{
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Offset(0x1A), // SLSTS - Slot Status Register
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ABP0, 1, // Bit 0, Attention Button Pressed
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, 2,
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PDC0, 1, // Bit 3, Presence Detect Changed
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, 2,
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PDS0, 1, // Bit 6, Presence Detect State
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, 1,
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LSC0, 1, // Bit 8, Link Active State Changed
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offset (0x20),
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, 16,
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PMS0, 1, // Bit 16, PME Status
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offset (0x98),
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, 30,
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HPE0, 1, // Bit 30, Hot Plug SCI Enable
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PCE0, 1, // Bit 31, Power Management SCI Enable.
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, 30,
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HPS0, 1, // Bit 30, Hot Plug SCI Status
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PCS0, 1, // Bit 31, Power Management SCI Status.
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}
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Method(_PRT,0,NotSerialized) {
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If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
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{
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Return (
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Package()
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{
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// Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
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Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1
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Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},
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Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},
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Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},
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}
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)
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}
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else // IOAPIC Routing
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{
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Return (
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Package()
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{
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// Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
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Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1
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Package() {0x0000ffff, 1, 0, 21},
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Package() {0x0000ffff, 2, 0, 22},
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Package() {0x0000ffff, 3, 0, 23},
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}
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)
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}
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}
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}
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Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1]
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{
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Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1
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Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
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OperationRegion (PES1,PCI_Config,0x40,0xA0)
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Field (PES1, AnyAcc, NoLock, Preserve)
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{
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Offset(0x1A), // SLSTS - Slot Status Register
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ABP1, 1, // Bit 0, Attention Button Pressed
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, 2,
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PDC1, 1, // Bit 3, Presence Detect Changed
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, 2,
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PDS1, 1, // Bit 6, Presence Detect State
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, 1,
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LSC1, 1, // Bit 8, Link Active State Changed
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offset (0x20),
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, 16,
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PMS1, 1, // Bit 16, PME Status
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offset (0x98),
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, 30,
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HPE1, 1, // Bit 30, Hot Plug SCI Enable
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PCE1, 1, // Bit 31, Power Management SCI Enable.
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, 30,
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HPS1, 1, // Bit 30, Hot Plug SCI Status
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PCS1, 1, // Bit 31, Power Management SCI Status.
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}
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Method(_PRT,0,NotSerialized) {
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If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
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{
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Return (
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Package()
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{
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// Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
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Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},
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Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},
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Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},
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Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},
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}
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)
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}
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else // IOAPIC Routing
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{
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Return (
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Package()
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{
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// Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
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Package() {0x0000ffff, 0, 0, 21},
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Package() {0x0000ffff, 1, 0, 22},
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Package() {0x0000ffff, 2, 0, 23},
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Package() {0x0000ffff, 3, 0, 20},
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}
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)
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}
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}
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}
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#endif
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