3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
76 lines
1.8 KiB
C
76 lines
1.8 KiB
C
/**
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**/
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/**
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Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@file
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PchUsbPolicy.h
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@brief
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PCH Usb policy PPI produced by a platform driver specifying
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various expected PCH Usb settings. This PPI is consumed by the
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PCH PEI drivers.
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**/
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#ifndef _PCH_USB_POLICY_H_
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#define _PCH_USB_POLICY_H_
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//
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// PCH Usb policy provided by platform for PEI phase
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//
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#ifndef ECP_FLAG
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#include <PiPei.h>
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#endif
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#include "PchRegs.h"
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#include <Protocol/PchPlatformPolicy.h>
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#define PCH_USB_POLICY_PPI_GUID \
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{ \
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0xc02b0573, 0x2b4e, 0x4a31, 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c \
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}
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extern EFI_GUID gPchUsbPolicyPpiGuid;
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typedef struct _PCH_USB_POLICY_PPI PCH_USB_POLICY_PPI;
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///
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/// PPI revision number
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/// Any backwards compatible changes to this PPI will result in an update in the revision number
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/// Major changes will require publication of a new PPI
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///
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/// Revision 1: Original version
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///
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#define PCH_USB_POLICY_PPI_REVISION_1 1
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///
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/// Generic definitions for device enabling/disabling used by PCH code.
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///
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#define PCH_DEVICE_ENABLE 1
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#define PCH_DEVICE_DISABLE 0
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#define EHCI_MODE 1
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struct _PCH_USB_POLICY_PPI {
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UINT8 Revision;
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PCH_USB_CONFIG *UsbConfig;
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UINT8 Mode;
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UINTN EhciMemBaseAddr;
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UINT32 EhciMemLength;
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UINTN XhciMemBaseAddr;
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};
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#endif
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