c7ed09e34b
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9913 6f19259b-4bc3-4df7-8a09-765794883524
537 lines
19 KiB
C
537 lines
19 KiB
C
/** @file
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Default exception handler
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Copyright (c) 2008-2010, Apple Inc. All rights reserved.
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/BaseLib.h>
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#include <Library/PrintLib.h>
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extern CHAR8 *gCondition[];
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extern CHAR8 *gReg[];
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#define LOAD_STORE_FORMAT1 1
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#define LOAD_STORE_FORMAT2 2
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#define LOAD_STORE_FORMAT3 3
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#define LOAD_STORE_FORMAT4 4
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#define LOAD_STORE_MULTIPLE_FORMAT1 5
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#define PUSH_FORMAT 6
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#define POP_FORMAT 106
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#define IMMED_8 7
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#define CONDITIONAL_BRANCH 8
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#define UNCONDITIONAL_BRANCH 9
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#define UNCONDITIONAL_BRANCH_SHORT 109
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#define BRANCH_EXCHANGE 10
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#define DATA_FORMAT1 11
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#define DATA_FORMAT2 12
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#define DATA_FORMAT3 13
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#define DATA_FORMAT4 14
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#define DATA_FORMAT5 15
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#define DATA_FORMAT6_SP 16
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#define DATA_FORMAT6_PC 116
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#define DATA_FORMAT7 17
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#define DATA_FORMAT8 19
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#define CPS_FORMAT 20
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#define ENDIAN_FORMAT 21
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#define B_T3 200
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#define B_T4 201
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#define BL_T2 202
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typedef struct {
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CHAR8 *Start;
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UINT32 OpCode;
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UINT32 Mask;
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UINT32 AddressMode;
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} THUMB_INSTRUCTIONS;
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THUMB_INSTRUCTIONS gOpThumb[] = {
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// Thumb 16-bit instrucitons
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// Op Mask Format
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{ "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 },
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{ "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },
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{ "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },
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{ "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },
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{ "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
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{ "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },
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{ "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },
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{ "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },
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{ "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },
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{ "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },
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{ "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },
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{ "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH },
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{ "B" , 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT },
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{ "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },
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{ "BX" , 0x4700, 0xff87, BRANCH_EXCHANGE },
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{ "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },
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{ "BKPT", 0xdf00, 0xff00, IMMED_8 },
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{ "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },
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{ "CMP" , 0x2800, 0xf800, DATA_FORMAT3 },
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{ "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },
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{ "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },
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{ "CPS" , 0xb660, 0xffe8, CPS_FORMAT },
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{ "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
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{ "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },
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{ "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
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{ "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 },
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{ "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
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{ "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },
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{ "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1 },
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{ "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1 },
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{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
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{ "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },
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{ "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
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{ "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },
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{ "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },
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{ "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },
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{ "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },
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{ "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
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{ "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },
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{ "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },
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{ "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },
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{ "ORR" , 0x4180, 0xffc0, DATA_FORMAT5 },
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{ "POP" , 0xbc00, 0xfe00, POP_FORMAT },
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{ "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },
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{ "REV" , 0xba00, 0xffc0, DATA_FORMAT5 },
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{ "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },
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{ "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },
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{ "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5 },
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{ "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
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{ "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },
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{ "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
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{ "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 },
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{ "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },
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{ "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },
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{ "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1 },
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{ "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1 },
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{ "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },
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{ "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },
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{ "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },
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{ "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },
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{ "SWI" , 0xdf00, 0xff00, IMMED_8 },
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{ "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
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{ "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
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{ "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },
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{ "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
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{ "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 }
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};
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THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "B", 0xf0008000, 0xf800d000, B_T3 },
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{ "B", 0xf0009000, 0xf800d000, B_T4 },
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{ "BL", 0xf000d000, 0xf800d000, B_T4 },
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{ "BLX", 0xf000c000, 0xf800d000, BL_T2 }
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// ADD POP PUSH STR(B)(D) LDR(B)(D) EOR MOV ADDS SUBS STM
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#if 0
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// 32-bit Thumb instructions op1 01
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// 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx Load/store multiple
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{ "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
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{ "SRS" , 0xe98dc000, 0xffdffff0, SRS_IA_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
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{ "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}
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{ "RFE" , 0xe990c000, 0xffd0ffff, RFE_IA_FORMAT }, // RFE{IA}<c> <Rn>{!}
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{ "STM" , 0xe8800000, 0xffd00000, STM_FORMAT }, // STM<c>.W <Rn>{!},<registers>
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{ "LDM" , 0xe8900000, 0xffd00000, STM_FORMAT }, // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
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{ "POP" , 0xe8bd0000, 0xffff2000, REGLIST_FORMAT }, // POP<c>.W <registers> >1 register
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{ "POP" , 0xf85d0b04, 0xffff0fff, RT_FORMAT }, // POP<c>.W <registers> 1 register
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{ "STMDB", 0xe9000000, 0xffd00000, STM_FORMAT }, // STMDB
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{ "PUSH" , 0xe8bd0000, 0xffffa000, REGLIST_FORMAT }, // PUSH<c>.W <registers> >1 register
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{ "PUSH" , 0xf84d0b04, 0xffff0fff, RT_FORMAT }, // PUSH<c>.W <registers> 1 register
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{ "LDMDB", 0xe9102000, 0xffd02000, STM_FORMAT }, // LDMDB<c> <Rn>{!},<registers>
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// 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx Load/store dual,
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{ "STREX" , 0xe0400000, 0xfff000f0, 3REG_IMM8_FORMAT }, // STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
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{ "STREXB", 0xe8c00f40, 0xfff00ff0, 3REG_FORMAT }, // STREXB<c> <Rd>,<Rt>,[<Rn>]
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{ "STREXD", 0xe8c00070, 0xfff000f0, 4REG_FORMAT }, // STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
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{ "STREXH", 0xe8c00f70, 0xfff00ff0, 3REG_FORMAT }, // STREXH<c> <Rd>,<Rt>,[<Rn>]
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{ "STRH", 0xf8c00000, 0xfff00000, 2REG_IMM8_FORMAT }, // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
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{ "STRH", 0xf8200000, 0xfff00000, }, // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
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// 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx Data-processing
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// 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
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// 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing modified immediate
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// 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing plain immediate
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// 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx Branches
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// 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx Store single data item
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// 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx SIMD or load/store
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// 1111 100x x001 xxxx xxxx xxxx xxxx xxxx Load byte, memory hints
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// 1111 100x x011 xxxx xxxx xxxx xxxx xxxx Load halfword, memory hints
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// 1111 100x x101 xxxx xxxx xxxx xxxx xxxx Load word
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// 1111 1 010 xxxx xxxx xxxx xxxx xxxx xxxx Data-processing register
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// 1111 1 011 0xxx xxxx xxxx xxxx xxxx xxxx Multiply
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// 1111 1 011 1xxx xxxx xxxx xxxx xxxx xxxx Long Multiply
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// 1111 1 1xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
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#endif
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};
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CHAR8 mThumbMregListStr[4*15 + 1];
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CHAR8 *
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ThumbMRegList (
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UINT32 RegBitMask
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)
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{
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UINTN Index, Start, End;
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CHAR8 *Str;
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BOOLEAN First;
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Str = mThumbMregListStr;
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*Str = '\0';
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AsciiStrCat (Str, "{");
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// R0 - R7, PC
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for (Index = 0, First = TRUE; Index <= 15; Index++) {
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if ((RegBitMask & (1 << Index)) != 0) {
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Start = End = Index;
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for (Index++; ((RegBitMask & (1 << Index)) != 0) && (Index <= 9); Index++) {
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End = Index;
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}
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if (!First) {
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AsciiStrCat (Str, ",");
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} else {
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First = FALSE;
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}
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if (Start == End) {
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AsciiStrCat (Str, gReg[Start]);
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} else {
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AsciiStrCat (Str, gReg[Start]);
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AsciiStrCat (Str, "-");
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AsciiStrCat (Str, gReg[End]);
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}
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}
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}
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if (First) {
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AsciiStrCat (Str, "ERROR");
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}
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AsciiStrCat (Str, "}");
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// BugBug: Make caller pass in buffer it is cleaner
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return mThumbMregListStr;
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}
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UINT32
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SignExtend32 (
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IN UINT32 Data,
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IN UINT32 TopBit
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)
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{
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if (((Data & TopBit) == 0) || (TopBit == BIT31)) {
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return Data;
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}
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do {
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TopBit <<= 1;
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Data |= TopBit;
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} while ((TopBit & BIT31) != BIT31);
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return Data;
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}
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/**
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Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
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point to next instructin.
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We cheat and only decode instructions that access
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memory. If the instruction is not found we dump the instruction in hex.
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@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
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@param Buf Buffer to sprintf disassembly into.
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@param Size Size of Buf in bytes.
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@param Extended TRUE dump hex for instruction too.
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**/
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VOID
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DisassembleThumbInstruction (
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IN UINT16 **OpCodePtrPtr,
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OUT CHAR8 *Buf,
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OUT UINTN Size,
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IN BOOLEAN Extended
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)
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{
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UINT16 *OpCodePtr;
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UINT16 OpCode;
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UINT32 OpCode32;
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UINT32 Index;
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UINT32 Offset;
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UINT16 Rd, Rn, Rm;
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BOOLEAN H1, H2, imod;
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UINT32 PC, Target;
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CHAR8 *Cond;
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BOOLEAN S, J1, J2;
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OpCodePtr = *OpCodePtrPtr;
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OpCode = **OpCodePtrPtr;
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// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
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OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);
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// These register names match branch form, but not others
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Rd = OpCode & 0x7;
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Rn = (OpCode >> 3) & 0x7;
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Rm = (OpCode >> 6) & 0x7;
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H1 = (OpCode & BIT7) != 0;
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H2 = (OpCode & BIT6) != 0;
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imod = (OpCode & BIT4) != 0;
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PC = (UINT32)(UINTN)OpCodePtr;
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// Increment by the minimum instruction size, Thumb2 could be bigger
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*OpCodePtrPtr += 1;
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for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {
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if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {
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if (Extended) {
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Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode, gOpThumb[Index].Start);
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} else {
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Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);
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}
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switch (gOpThumb[Index].AddressMode) {
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case LOAD_STORE_FORMAT1:
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// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
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return;
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case LOAD_STORE_FORMAT2:
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// A6.5.1 <Rd>, [<Rn>, <Rm>]
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
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return;
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case LOAD_STORE_FORMAT3:
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// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
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Target = (OpCode & 0xff) << 2;
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PC + 4 + Target);
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return;
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case LOAD_STORE_FORMAT4:
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// Rt, [SP, #imm8]
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Target = (OpCode & 0xff) << 2;
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target, PC + 3 + Target);
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return;
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case LOAD_STORE_MULTIPLE_FORMAT1:
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// <Rn>!, {r0-r7}
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
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return;
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case POP_FORMAT:
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// POP {r0-r7,pc}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
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return;
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case PUSH_FORMAT:
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// PUSH {r0-r7,lr}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
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return;
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case IMMED_8:
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// A6.7 <immed_8>
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
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return;
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case CONDITIONAL_BRANCH:
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// A6.3.1 B<cond> <target_address>
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// Patch in the condition code. A little hack but based on "%-6a"
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Cond = gCondition[(OpCode >> 8) & 0xf];
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Buf[Offset-5] = *Cond++;
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Buf[Offset-4] = *Cond;
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
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return;
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case UNCONDITIONAL_BRANCH_SHORT:
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// A6.3.2 B <target_address>
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
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return;
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case BRANCH_EXCHANGE:
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// A6.3.3 BX|BLX <Rm>
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
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return;
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case DATA_FORMAT1:
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// A6.4.3 <Rd>, <Rn>, <Rm>
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
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return;
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case DATA_FORMAT2:
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// A6.4.3 <Rd>, <Rn>, #3_bit_immed
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
|
|
return;
|
|
case DATA_FORMAT3:
|
|
// A6.4.3 <Rd>|<Rn>, #imm8
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
|
|
return;
|
|
case DATA_FORMAT4:
|
|
// A6.4.3 <Rd>|<Rm>, #immed_5
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
|
|
return;
|
|
case DATA_FORMAT5:
|
|
// A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
|
|
return;
|
|
case DATA_FORMAT6_SP:
|
|
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
|
|
return;
|
|
case DATA_FORMAT6_PC:
|
|
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
|
|
return;
|
|
case DATA_FORMAT7:
|
|
// A6.4.3 SP, SP, #<7_Bit_immed>
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
|
|
return;
|
|
case DATA_FORMAT8:
|
|
// A6.4.3 <Rd>|<Rn>, <Rm>
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
|
|
return;
|
|
|
|
case CPS_FORMAT:
|
|
// A7.1.24
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
|
|
return;
|
|
|
|
case ENDIAN_FORMAT:
|
|
// A7.1.24
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// Thumb2 are 32-bit instructions
|
|
*OpCodePtrPtr += 1;
|
|
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
|
|
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {
|
|
if (Extended) {
|
|
Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode32, gOpThumb2[Index].Start);
|
|
} else {
|
|
Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);
|
|
}
|
|
switch (gOpThumb2[Index].AddressMode) {
|
|
case B_T3:
|
|
Cond = gCondition[(OpCode32 >> 22) & 0xf];
|
|
Buf[Offset-5] = *Cond++;
|
|
Buf[Offset-4] = *Cond;
|
|
// S:J2:J1:imm6:imm11:0
|
|
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3f000);
|
|
Target |= ((OpCode32 & BIT11) == BIT11)? BIT19 : 0; // J2
|
|
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
|
|
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
|
|
Target = SignExtend32 (Target, BIT20);
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
|
return;
|
|
case B_T4:
|
|
// S:I1:I2:imm10:imm11:0
|
|
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
|
|
S = (OpCode32 & BIT26) == BIT26;
|
|
J1 = (OpCode32 & BIT13) == BIT13;
|
|
J2 = (OpCode32 & BIT11) == BIT11;
|
|
Target |= (!(J2 ^ S) ? BIT22 : 0); // I2
|
|
Target |= (!(J1 ^ S) ? BIT23 : 0); // I1
|
|
Target |= (S ? BIT24 : 0); // S
|
|
Target = SignExtend32 (Target, BIT24);
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
|
return;
|
|
|
|
case BL_T2:
|
|
// S:I1:I2:imm10:imm11:00
|
|
Target = ((OpCode32 << 2) & 0x1ffc) + ((OpCode32 >> 3) & 0x7fe000);
|
|
S = (OpCode32 & BIT26) == BIT26;
|
|
J1 = (OpCode32 & BIT13) == BIT13;
|
|
J2 = (OpCode32 & BIT11) == BIT11;
|
|
Target |= (!(J2 ^ S) ? BIT23 : 0); // I2
|
|
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1
|
|
Target |= (S ? BIT25 : 0); // S
|
|
Target = SignExtend32 (Target, BIT25);
|
|
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
AsciiSPrint (Buf, Size, "0x%08x", OpCode32);
|
|
}
|
|
|
|
|
|
|
|
VOID
|
|
DisassembleArmInstruction (
|
|
IN UINT32 **OpCodePtr,
|
|
OUT CHAR8 *Buf,
|
|
OUT UINTN Size,
|
|
IN BOOLEAN Extended
|
|
);
|
|
|
|
|
|
/**
|
|
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
|
|
point to next instructin.
|
|
|
|
We cheat and only decode instructions that access
|
|
memory. If the instruction is not found we dump the instruction in hex.
|
|
|
|
@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
|
|
@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
|
|
@param Extended TRUE dump hex for instruction too.
|
|
@param Buf Buffer to sprintf disassembly into.
|
|
@param Size Size of Buf in bytes.
|
|
|
|
**/
|
|
VOID
|
|
DisassembleInstruction (
|
|
IN UINT8 **OpCodePtr,
|
|
IN BOOLEAN Thumb,
|
|
IN BOOLEAN Extended,
|
|
OUT CHAR8 *Buf,
|
|
OUT UINTN Size
|
|
)
|
|
{
|
|
if (Thumb) {
|
|
DisassembleThumbInstruction ((UINT16 **)OpCodePtr, Buf, Size, Extended);
|
|
} else {
|
|
DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);
|
|
}
|
|
}
|
|
|