6b4483cdbd
1) XHCI host controller hw always provides more than 5 interrupters. Now using interrupter 0 to accommodate all received events. 2) XHCI host controller hw always provides 32bytes context size. Now it dynamically detect context size and construct it. also solved several issues: 1) Divides 64byte width register access to two 32bit registers access because some XHCI chipsets cannot support a single 64bit access. 2) Remove halt host controller statement in UsbBusDriverBindingStop(). It has been done by host controller’s DriverBindingStop(). And XhciDriverBindingStop() need XHCI host controller is in running state because it need execute DISABLE_SLOT cmd to release h/w resource. signed-off-by: erictian Reviewed-by: li-elvin git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12785 6f19259b-4bc3-4df7-8a09-765794883524
728 lines
18 KiB
C
728 lines
18 KiB
C
/** @file
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The XHCI register operation routines.
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Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "Xhci.h"
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/**
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Read 1-byte width XHCI capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 1-byte width capability register.
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@return The register content read.
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@retval If err, return 0xFF.
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**/
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UINT8
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XhcReadCapReg8 (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT8 Data;
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EFI_STATUS Status;
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint8,
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XHC_BAR_INDEX,
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(UINT64) Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
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Data = 0xFF;
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}
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return Data;
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}
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/**
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Read 4-bytes width XHCI capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 4-bytes width capability register.
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@return The register content read.
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@retval If err, return 0xFFFFFFFF.
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**/
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UINT32
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XhcReadCapReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Read 4-bytes width XHCI Operational register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 4-bytes width operational register.
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@return The register content read.
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@retval If err, return 0xFFFFFFFF.
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**/
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UINT32
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XhcReadOpReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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ASSERT (Xhc->CapLength != 0);
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->CapLength + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Write the data to the 4-bytes width XHCI operational register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 4-bytes width operational register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteOpReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->CapLength != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->CapLength + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Write the data to the 2-bytes width XHCI operational register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 2-bytes width operational register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteOpReg16 (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT16 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->CapLength != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint16,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->CapLength + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcWriteOpReg16: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Read XHCI door bell register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the door bell register.
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@return The register content read
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**/
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UINT32
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XhcReadDoorBellReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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ASSERT (Xhc->DBOff != 0);
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->DBOff + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcReadDoorBellReg: Pci Io Read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Write the data to the XHCI door bell register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the door bell register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteDoorBellReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->DBOff != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->DBOff + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Read XHCI runtime register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the runtime register.
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@return The register content read
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**/
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UINT32
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XhcReadRuntimeReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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ASSERT (Xhc->RTSOff != 0);
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->RTSOff + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Write the data to the XHCI runtime register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the runtime register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteRuntimeReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->RTSOff != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->RTSOff + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Read XHCI extended capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the extended capability register.
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@return The register content read
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**/
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UINT32
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XhcReadExtCapReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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ASSERT (Xhc->ExtCapRegBase != 0);
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->ExtCapRegBase + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Write the data to the XHCI extended capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the extended capability register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteExtCapReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->ExtCapRegBase != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64) (Xhc->ExtCapRegBase + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Set one bit of the runtime register while keeping other bits.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the runtime register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcSetRuntimeRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = XhcReadRuntimeReg (Xhc, Offset);
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Data |= Bit;
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XhcWriteRuntimeReg (Xhc, Offset, Data);
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}
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/**
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Clear one bit of the runtime register while keeping other bits.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the runtime register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcClearRuntimeRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = XhcReadRuntimeReg (Xhc, Offset);
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Data &= ~Bit;
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XhcWriteRuntimeReg (Xhc, Offset, Data);
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}
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/**
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Set one bit of the operational register while keeping other bits.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the operational register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcSetOpRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = XhcReadOpReg (Xhc, Offset);
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Data |= Bit;
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XhcWriteOpReg (Xhc, Offset, Data);
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}
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/**
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Clear one bit of the operational register while keeping other bits.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the operational register.
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@param Bit The bit mask of the register to clear.
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**/
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VOID
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XhcClearOpRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = XhcReadOpReg (Xhc, Offset);
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Data &= ~Bit;
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XhcWriteOpReg (Xhc, Offset, Data);
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}
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/**
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Wait the operation register's bit as specified by Bit
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to become set (or clear).
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@param Xhc The XHCI Instance.
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@param Offset The offset of the operation register.
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@param Bit The bit of the register to wait for.
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@param WaitToSet Wait the bit to set or clear.
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@param Timeout The time to wait before abort (in millisecond, ms).
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@retval EFI_SUCCESS The bit successfully changed by host controller.
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@retval EFI_TIMEOUT The time out occurred.
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**/
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EFI_STATUS
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XhcWaitOpRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit,
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IN BOOLEAN WaitToSet,
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IN UINT32 Timeout
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)
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{
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UINT32 Index;
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UINTN Loop;
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Loop = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;
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for (Index = 0; Index < Loop; Index++) {
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if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {
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return EFI_SUCCESS;
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}
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gBS->Stall (XHC_POLL_DELAY);
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}
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return EFI_TIMEOUT;
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}
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/**
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Set Bios Ownership
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@param Xhc The XHCI Instance.
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**/
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VOID
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XhcSetBiosOwnership (
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IN USB_XHCI_INSTANCE *Xhc
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)
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{
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UINT32 Buffer;
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DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
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Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
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Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);
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XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);
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}
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/**
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Clear Bios Ownership
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@param Xhc The XHCI Instance.
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**/
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VOID
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XhcClearBiosOwnership (
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IN USB_XHCI_INSTANCE *Xhc
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)
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{
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UINT32 Buffer;
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DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
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Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
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Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);
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XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);
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}
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/**
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Calculate the XHCI legacy support capability register offset.
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@param Xhc The XHCI Instance.
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@return The offset of XHCI legacy support capability register.
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**/
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UINT32
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XhcGetLegSupCapAddr (
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IN USB_XHCI_INSTANCE *Xhc
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)
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{
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UINT32 ExtCapOffset;
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UINT8 NextExtCapReg;
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UINT32 Data;
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ExtCapOffset = 0;
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do {
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//
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// Check if the extended capability register's capability id is USB Legacy Support.
|
|
//
|
|
Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
|
|
if ((Data & 0xFF) == 0x1) {
|
|
return ExtCapOffset;
|
|
}
|
|
//
|
|
// If not, then traverse all of the ext capability registers till finding out it.
|
|
//
|
|
NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);
|
|
ExtCapOffset += (NextExtCapReg << 2);
|
|
} while (NextExtCapReg != 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
Whether the XHCI host controller is halted.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
|
|
@retval TRUE The controller is halted.
|
|
@retval FALSE It isn't halted.
|
|
|
|
**/
|
|
BOOLEAN
|
|
XhcIsHalt (
|
|
IN USB_XHCI_INSTANCE *Xhc
|
|
)
|
|
{
|
|
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
|
|
}
|
|
|
|
|
|
/**
|
|
Whether system error occurred.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
|
|
@retval TRUE System error happened.
|
|
@retval FALSE No system error.
|
|
|
|
**/
|
|
BOOLEAN
|
|
XhcIsSysError (
|
|
IN USB_XHCI_INSTANCE *Xhc
|
|
)
|
|
{
|
|
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
|
|
}
|
|
|
|
/**
|
|
Reset the XHCI host controller.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param Timeout Time to wait before abort (in millisecond, ms).
|
|
|
|
@retval EFI_SUCCESS The XHCI host controller is reset.
|
|
@return Others Failed to reset the XHCI before Timeout.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
XhcResetHC (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT32 Timeout
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
|
|
//
|
|
// Host can only be reset when it is halt. If not so, halt it
|
|
//
|
|
if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
|
|
Status = XhcHaltHC (Xhc, Timeout);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
return Status;
|
|
}
|
|
}
|
|
|
|
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
|
|
Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
|
|
return Status;
|
|
}
|
|
|
|
|
|
/**
|
|
Halt the XHCI host controller.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param Timeout Time to wait before abort (in millisecond, ms).
|
|
|
|
@return EFI_SUCCESS The XHCI host controller is halt.
|
|
@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
XhcHaltHC (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT32 Timeout
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
|
|
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
|
|
return Status;
|
|
}
|
|
|
|
|
|
/**
|
|
Set the XHCI host controller to run.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param Timeout Time to wait before abort (in millisecond, ms).
|
|
|
|
@return EFI_SUCCESS The XHCI host controller is running.
|
|
@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
XhcRunHC (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT32 Timeout
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
|
|
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
|
|
return Status;
|
|
}
|
|
|