f220dcbba8
During CpuDxe initialization, MMU will be setup with the highest mode that HW supports. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
69 lines
1.4 KiB
C
69 lines
1.4 KiB
C
/** @file
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Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
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Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef BASE_RISCV_MMU_LIB_H_
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#define BASE_RISCV_MMU_LIB_H_
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/**
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The API to flush all local TLBs.
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**/
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VOID
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EFIAPI
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RiscVLocalTlbFlushAll (
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VOID
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);
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/**
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The API to flush local TLB at a virtual address.
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@param VirtAddr The virtual address.
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**/
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VOID
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EFIAPI
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RiscVLocalTlbFlush (
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UINTN VirtAddr
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);
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/**
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The API to set a GCD attribute on an memory region.
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@param BaseAddress The base address of the region.
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@param Length The length of the region.
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@param Attributes The GCD attributes.
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@retval EFI_INVALID_PARAMETER The BaseAddress or Length was not valid.
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@retval EFI_OUT_OF_RESOURCES Not enough resource.
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@retval EFI_SUCCESS The operation succesfully.
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**/
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EFI_STATUS
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EFIAPI
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RiscVSetMemoryAttributes (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 Attributes
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);
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/**
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The API to configure and enable RISC-V MMU with the highest mode supported.
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@retval EFI_OUT_OF_RESOURCES Not enough resource.
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@retval EFI_SUCCESS The operation succesfully.
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**/
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EFI_STATUS
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EFIAPI
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RiscVConfigureMmu (
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VOID
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);
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#endif /* BASE_RISCV_MMU_LIB_H_ */
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