c9f231d08b
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
91 lines
2.0 KiB
C
91 lines
2.0 KiB
C
/** @file
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File to contain all the hardware specific stuff for the Smm Sw dispatch protocol.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Include common header file for this module.
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//
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#include "CommonHeader.h"
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#include "QNCSmmHelpers.h"
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EFI_SMM_CPU_PROTOCOL *mSmmCpu = NULL;
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CONST QNC_SMM_SOURCE_DESC SW_SOURCE_DESC = {
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QNC_SMM_NO_FLAGS,
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{
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{
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{GPE_ADDR_TYPE, {R_QNC_GPE0BLK_SMIE}}, S_QNC_GPE0BLK_SMIE, N_QNC_GPE0BLK_SMIE_APM
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},
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NULL_BIT_DESC_INITIALIZER
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},
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{
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{
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{GPE_ADDR_TYPE, {R_QNC_GPE0BLK_SMIS}}, S_QNC_GPE0BLK_SMIS, N_QNC_GPE0BLK_SMIS_APM
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}
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}
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};
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VOID
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SwGetContext(
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IN DATABASE_RECORD *Record,
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OUT QNC_SMM_CONTEXT *Context
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)
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{
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Context->Sw.SwSmiInputValue = IoRead8 (R_APM_CNT);
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}
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BOOLEAN
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SwCmpContext (
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IN QNC_SMM_CONTEXT *Context1,
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IN QNC_SMM_CONTEXT *Context2
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)
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{
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return (BOOLEAN)( Context1->Sw.SwSmiInputValue == Context2->Sw.SwSmiInputValue );
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}
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VOID
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SwGetBuffer (
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IN DATABASE_RECORD * Record
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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UINTN CpuIndex;
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EFI_SMM_SAVE_STATE_IO_INFO IoState;
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//
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// Locate SMM CPU protocol to retrieve the CPU save state
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//
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if (mSmmCpu == NULL) {
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Status = gSmst->SmmLocateProtocol (&gEfiSmmCpuProtocolGuid, NULL, (VOID **) &mSmmCpu);
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ASSERT_EFI_ERROR (Status);
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}
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//
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// Find the CPU which generated the software SMI
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//
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CpuIndex = 0;
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for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
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Status = mSmmCpu->ReadSaveState (
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mSmmCpu,
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sizeof (EFI_SMM_SAVE_STATE_IO_INFO),
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EFI_SMM_SAVE_STATE_REGISTER_IO,
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Index,
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&IoState
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);
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if (!EFI_ERROR (Status) && (IoState.IoPort == R_APM_CNT)) {
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CpuIndex = Index;
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break;
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}
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}
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Record->CommBuffer.Sw.SwSmiCpuIndex = CpuIndex;
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}
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