c9f231d08b
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
148 lines
3.3 KiB
C
148 lines
3.3 KiB
C
/** @file
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File to contain all the hardware specific stuff for the Smm Sx dispatch protocol.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Include common header file for this module.
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//
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#include "CommonHeader.h"
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#include "QNCSmmHelpers.h"
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CONST QNC_SMM_SOURCE_DESC SX_SOURCE_DESC = {
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QNC_SMM_NO_FLAGS,
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{
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{
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{GPE_ADDR_TYPE, {R_QNC_GPE0BLK_SMIE}}, S_QNC_GPE0BLK_SMIE, N_QNC_GPE0BLK_SMIE_SLP
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},
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NULL_BIT_DESC_INITIALIZER
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},
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{
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{
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{GPE_ADDR_TYPE, {R_QNC_GPE0BLK_SMIS}}, S_QNC_GPE0BLK_SMIS, N_QNC_GPE0BLK_SMIS_SLP
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}
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}
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};
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VOID
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SxGetContext(
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IN DATABASE_RECORD *Record,
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OUT QNC_SMM_CONTEXT *Context
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)
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{
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UINT32 Pm1Cnt;
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Pm1Cnt = IoRead32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);
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//
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// By design, the context phase will always be ENTRY
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//
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Context->Sx.Phase = SxEntry;
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//
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// Map the PM1_CNT register's SLP_TYP bits to the context type
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//
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switch (Pm1Cnt & B_QNC_PM1BLK_PM1C_SLPTP) {
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case V_S0:
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Context->Sx.Type = SxS0;
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break;
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case V_S3:
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Context->Sx.Type = SxS3;
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break;
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case V_S4:
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Context->Sx.Type = SxS4;
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break;
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case V_S5:
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Context->Sx.Type = SxS5;
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break;
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default:
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ASSERT (FALSE);
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break;
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};
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}
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BOOLEAN
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SxCmpContext (
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IN QNC_SMM_CONTEXT *Context1,
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IN QNC_SMM_CONTEXT *Context2
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)
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{
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return (BOOLEAN)(Context1->Sx.Type == Context2->Sx.Type);
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}
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VOID
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QNCSmmSxGoToSleep(
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VOID
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)
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/*++
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Routine Description:
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When we get an SMI that indicates that we are transitioning to a sleep state,
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we need to actually transition to that state. We do this by disabling the
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"SMI on sleep enable" feature, which generates an SMI when the operating system
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tries to put the system to sleep, and then physically putting the system to sleep.
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Returns:
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None.
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--*/
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{
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UINT32 Pm1Cnt;
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//
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// Flush cache into memory before we go to sleep. It is necessary for S3 sleep
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// because we may update memory in SMM Sx sleep handlers -- the updates are in cache now
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//
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AsmWbinvd();
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//
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// Disable SMIs
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//
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QNCSmmClearSource (&SX_SOURCE_DESC );
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QNCSmmDisableSource (&SX_SOURCE_DESC);
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//
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// Clear Sleep Type Enable
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//
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IoAnd16 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIE, (UINT16)(~B_QNC_GPE0BLK_SMIE_SLP));
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// clear sleep SMI status
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IoAnd16 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS, (UINT16)(S_QNC_GPE0BLK_SMIS));
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//
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// Now that SMIs are disabled, write to the SLP_EN bit again to trigger the sleep
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//
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Pm1Cnt = IoOr32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, B_QNC_PM1BLK_PM1C_SLPEN);
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//
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// The system just went to sleep. If the sleep state was S1, then code execution will resume
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// here when the system wakes up.
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//
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Pm1Cnt = IoRead32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);
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if ((Pm1Cnt & B_QNC_PM1BLK_PM1C_SCIEN) == 0) {
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//
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// An ACPI OS isn't present, clear the sleep information
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//
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Pm1Cnt &= ~B_QNC_PM1BLK_PM1C_SLPTP;
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Pm1Cnt |= V_S0;
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IoWrite32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, Pm1Cnt);
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}
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QNCSmmClearSource (&SX_SOURCE_DESC);
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QNCSmmEnableSource (&SX_SOURCE_DESC);
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}
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