9d510e61fc
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
90 lines
3.6 KiB
C
90 lines
3.6 KiB
C
/** @file
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EFI SMM Control PPI definition.
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This PPI is used to initiate SMI/PMI activations. This protocol could be published by either:
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- A processor driver to abstract the SMI/PMI IPI
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- The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an
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Intel chipset
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Because of the possibility of performing SMI or PMI IPI transactions, the ability to generate this
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event from a platform chipset agent is an optional capability for both IA-32 and Itanium-based
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systems.
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Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SMM_CONTROL_PPI_H_
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#define _SMM_CONTROL_PPI_H_
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#define PEI_SMM_CONTROL_PPI_GUID \
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{ 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }
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typedef struct _PEI_SMM_CONTROL_PPI PEI_SMM_CONTROL_PPI;
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/**
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Invokes SMI activation from either the preboot or runtime environment.
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@param PeiServices General purpose services available to every PEIM.
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@param This The PEI_SMM_CONTROL_PPI instance.
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@param ArgumentBuffer The optional sized data to pass into the protocol activation.
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@param ArgumentBufferSize The optional size of the data.
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@param Periodic An optional mechanism to periodically repeat activation.
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@param ActivationInterval An optional parameter to repeat at this period one
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time or, if the Periodic Boolean is set, periodically.
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@retval EFI_SUCCESS The SMI/PMI has been engendered.
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@retval EFI_DEVICE_ERROR The timing is unsupported.
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@retval EFI_INVALID_PARAMETER The activation period is unsupported.
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@retval EFI_NOT_STARTED The SMM base service has not been initialized.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *PEI_SMM_ACTIVATE) (
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_SMM_CONTROL_PPI * This,
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IN OUT INT8 *ArgumentBuffer OPTIONAL,
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IN OUT UINTN *ArgumentBufferSize OPTIONAL,
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IN BOOLEAN Periodic OPTIONAL,
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IN UINTN ActivationInterval OPTIONAL
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);
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/**
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Clears any system state that was created in response to the Active call.
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@param PeiServices General purpose services available to every PEIM.
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@param This The PEI_SMM_CONTROL_PPI instance.
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@param Periodic Optional parameter to repeat at this period one
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time or, if the Periodic Boolean is set, periodically.
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@retval EFI_SUCCESS The SMI/PMI has been engendered.
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@retval EFI_DEVICE_ERROR The source could not be cleared.
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@retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *PEI_SMM_DEACTIVATE) (
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_SMM_CONTROL_PPI * This,
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IN BOOLEAN Periodic OPTIONAL
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);
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///
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/// PEI SMM Control PPI is used to initiate SMI/PMI activations. This protocol could be published by either:
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/// - A processor driver to abstract the SMI/PMI IPI
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/// - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an
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/// Intel chipset
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///
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struct _PEI_SMM_CONTROL_PPI {
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PEI_SMM_ACTIVATE Trigger;
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PEI_SMM_DEACTIVATE Clear;
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};
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extern EFI_GUID gPeiSmmControlPpiGuid;
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#endif
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