50255363cb
Stack guard feature makes use of paging mechanism to monitor if there's a stack overflow occurred during boot. This patch will check setting of PCD PcdCpuStackGuard. If it's TRUE, DxeIpl will setup page table and set the page at which the stack base locates to be NOT PRESENT. If stack is used up and memory access cross into the last page of it, #PF exception will be triggered. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
/** @file
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x64-specifc functionality for DxeLoad.
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "DxeIpl.h"
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#include "X64/VirtualMemory.h"
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/**
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Transfers control to DxeCore.
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This function performs a CPU architecture specific operations to execute
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the entry point of DxeCore with the parameters of HobList.
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It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
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@param DxeCoreEntryPoint The entry point of DxeCore.
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@param HobList The start of HobList passed to DxeCore.
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**/
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VOID
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HandOffToDxeCore (
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IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
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IN EFI_PEI_HOB_POINTERS HobList
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)
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{
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VOID *BaseOfStack;
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VOID *TopOfStack;
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EFI_STATUS Status;
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UINTN PageTables;
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UINT32 Index;
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EFI_VECTOR_HANDOFF_INFO *VectorInfo;
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EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
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if (IsNullDetectionEnabled ()) {
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ClearFirst4KPage (HobList.Raw);
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}
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//
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// Get Vector Hand-off Info PPI and build Guided HOB
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//
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Status = PeiServicesLocatePpi (
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&gEfiVectorHandoffInfoPpiGuid,
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0,
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NULL,
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(VOID **)&VectorHandoffInfoPpi
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);
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if (Status == EFI_SUCCESS) {
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DEBUG ((EFI_D_INFO, "Vector Hand-off Info PPI is gotten, GUIDed HOB is created!\n"));
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VectorInfo = VectorHandoffInfoPpi->Info;
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Index = 1;
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while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {
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VectorInfo ++;
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Index ++;
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}
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BuildGuidDataHob (
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&gEfiVectorHandoffInfoPpiGuid,
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VectorHandoffInfoPpi->Info,
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sizeof (EFI_VECTOR_HANDOFF_INFO) * Index
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);
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}
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//
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// Allocate 128KB for the Stack
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//
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BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
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ASSERT (BaseOfStack != NULL);
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//
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// Compute the top of the stack we were allocated. Pre-allocate a UINTN
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// for safety.
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//
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TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
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TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
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PageTables = 0;
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if (FeaturePcdGet (PcdDxeIplBuildPageTables)) {
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//
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// Create page table and save PageMapLevel4 to CR3
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//
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PageTables = CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS) (UINTN) BaseOfStack, STACK_SIZE);
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} else {
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//
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// Set NX for stack feature also require PcdDxeIplBuildPageTables be TRUE
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// for the DxeIpl and the DxeCore are both X64.
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//
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ASSERT (PcdGetBool (PcdSetNxForStack) == FALSE);
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ASSERT (PcdGetBool (PcdCpuStackGuard) == FALSE);
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}
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//
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// End of PEI phase signal
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//
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Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
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ASSERT_EFI_ERROR (Status);
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if (FeaturePcdGet (PcdDxeIplBuildPageTables)) {
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AsmWriteCr3 (PageTables);
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}
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//
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// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
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//
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UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE);
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//
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// Transfer the control to the entry point of DxeCore.
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//
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SwitchStack (
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(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
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HobList.Raw,
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NULL,
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TopOfStack
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);
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}
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