6e601a4109
When StackGuard is enabled on IA32, the #double fault exception
is reported instead of #page fault.
This issue does not exist on X64, or IA32 without StackGuard.
The fix at e4435f710c was incomplete.
It is because AllocateCodePages() is used to allocate buffer for
GDT and TSS, the code pages will be set to RO in SetMemMapAttributes().
But IA32 Stack Guard need use task switch to switch stack that need
write GDT and TSS, so AllocateCodePages() could not be used.
This patch uses AllocatePages() instead of AllocateCodePages() to
allocate buffer for GDT and TSS if StackGuard is enabled on IA32.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
157 lines
4.5 KiB
C
157 lines
4.5 KiB
C
/** @file
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SMM CPU misc functions for x64 arch specific.
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Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PiSmmCpuDxeSmm.h"
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EFI_PHYSICAL_ADDRESS mGdtBuffer;
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UINTN mGdtBufferSize;
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/**
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Initialize IDT for SMM Stack Guard.
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**/
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VOID
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EFIAPI
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InitializeIDTSmmStackGuard (
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VOID
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)
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{
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IA32_IDT_GATE_DESCRIPTOR *IdtGate;
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//
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// If SMM Stack Guard feature is enabled, set the IST field of
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// the interrupt gate for Page Fault Exception to be 1
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//
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IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
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IdtGate += EXCEPT_IA32_PAGE_FAULT;
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IdtGate->Bits.Reserved_0 = 1;
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}
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/**
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Initialize Gdt for all processors.
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@param[in] Cr3 CR3 value.
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@param[out] GdtStepSize The step size for GDT table.
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@return GdtBase for processor 0.
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GdtBase for processor X is: GdtBase + (GdtStepSize * X)
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**/
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VOID *
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InitGdt (
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IN UINTN Cr3,
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OUT UINTN *GdtStepSize
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)
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{
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UINTN Index;
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IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
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UINTN TssBase;
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UINTN GdtTssTableSize;
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UINT8 *GdtTssTables;
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UINTN GdtTableStepSize;
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//
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// For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention
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// on each SMI entry.
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//
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GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned
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mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
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GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
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ASSERT (GdtTssTables != NULL);
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mGdtBuffer = (UINTN)GdtTssTables;
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GdtTableStepSize = GdtTssTableSize;
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for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
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CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);
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//
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// Fixup TSS descriptors
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//
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TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
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GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
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GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;
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GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);
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GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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//
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// Setup top of known good stack as IST1 for each processor.
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//
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*(UINTN *)(TssBase + TSS_X64_IST1_OFFSET) = (mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize);
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}
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}
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*GdtStepSize = GdtTableStepSize;
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return GdtTssTables;
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}
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/**
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Get Protected mode code segment from current GDT table.
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@return Protected mode code segment value.
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**/
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UINT16
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GetProtectedModeCS (
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VOID
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)
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{
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IA32_DESCRIPTOR GdtrDesc;
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IA32_SEGMENT_DESCRIPTOR *GdtEntry;
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UINTN GdtEntryCount;
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UINT16 Index;
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Index = (UINT16) -1;
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AsmReadGdtr (&GdtrDesc);
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GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
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GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;
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for (Index = 0; Index < GdtEntryCount; Index++) {
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if (GdtEntry->Bits.L == 0) {
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if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.L == 0) {
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break;
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}
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}
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GdtEntry++;
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}
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ASSERT (Index != -1);
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return Index * 8;
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}
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/**
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Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.
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@param[in] ApHltLoopCode The address of the safe hlt-loop function.
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@param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.
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@param[in] NumberToFinishAddress Address of Semaphore of APs finish count.
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**/
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VOID
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TransferApToSafeState (
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IN UINTN ApHltLoopCode,
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IN UINTN TopOfStack,
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IN UINTN NumberToFinishAddress
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)
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{
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AsmDisablePaging64 (
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GetProtectedModeCS (),
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(UINT32)ApHltLoopCode,
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(UINT32)NumberToFinishAddress,
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0,
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(UINT32)TopOfStack
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);
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//
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// It should never reach here
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//
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ASSERT (FALSE);
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}
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