ccf8184ac3
https://bugzilla.tianocore.org/show_bug.cgi?id=849
In V2, use "mov rax, strict qword 0" to replace the hard code db.
1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits.
This way is same to MpInitLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
(cherry picked from commit e21e355e2c)
# Conflicts:
# UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
385 lines
11 KiB
NASM
385 lines
11 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiException.nasm
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;
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; Abstract:
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;
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; Exception handlers used in SM mode
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;
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;-------------------------------------------------------------------------------
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extern ASM_PFX(SmiPFHandler)
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global ASM_PFX(gcSmiIdtr)
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global ASM_PFX(gcSmiGdtr)
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global ASM_PFX(gcPsd)
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SECTION .data
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NullSeg: DQ 0 ; reserved by architecture
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CodeSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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ProtModeCodeSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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ProtModeSsSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x93
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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DataSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x93
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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CodeSeg16:
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DW -1
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DW 0
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DB 0
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DB 0x9b
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DB 0x8f
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DB 0
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DataSeg16:
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DW -1
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DW 0
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DB 0
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DB 0x93
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DB 0x8f
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DB 0
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CodeSeg64:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xaf ; LimitHigh
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DB 0 ; BaseHigh
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; TSS Segment for X64 specially
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TssSeg:
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DW TSS_DESC_SIZE ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x89
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DB 0x80 ; LimitHigh
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DB 0 ; BaseHigh
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DD 0 ; BaseUpper
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DD 0 ; Reserved
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GDT_SIZE equ $ - NullSeg
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; Create TSS Descriptor just after GDT
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TssDescriptor:
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DD 0 ; Reserved
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DQ 0 ; RSP0
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DQ 0 ; RSP1
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DQ 0 ; RSP2
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DD 0 ; Reserved
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DD 0 ; Reserved
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DQ 0 ; IST1
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DQ 0 ; IST2
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DQ 0 ; IST3
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DQ 0 ; IST4
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DQ 0 ; IST5
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DQ 0 ; IST6
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DQ 0 ; IST7
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DD 0 ; Reserved
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DD 0 ; Reserved
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DW 0 ; Reserved
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DW 0 ; I/O Map Base Address
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TSS_DESC_SIZE equ $ - TssDescriptor
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;
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; This structure serves as a template for all processors.
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;
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ASM_PFX(gcPsd):
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DB 'PSDSIG '
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DW PSD_SIZE
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DW 2
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DW 1 << 2
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DW CODE_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW 0
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DQ 0
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DQ 0
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DQ 0 ; fixed in InitializeMpServiceData()
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DQ NullSeg
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DD GDT_SIZE
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DD 0
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times 24 DB 0
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DQ 0
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PSD_SIZE equ $ - ASM_PFX(gcPsd)
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;
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; CODE & DATA segments for SMM runtime
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;
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CODE_SEL equ CodeSeg64 - NullSeg
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DATA_SEL equ DataSeg32 - NullSeg
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CODE32_SEL equ CodeSeg32 - NullSeg
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ASM_PFX(gcSmiGdtr):
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DW GDT_SIZE - 1
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DQ NullSeg
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ASM_PFX(gcSmiIdtr):
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DW 0
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DQ 0
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DEFAULT REL
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SECTION .text
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;------------------------------------------------------------------------------
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; _SmiExceptionEntryPoints is the collection of exception entrypoints followed
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; by a common exception handler.
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;
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; Stack frame would be as follows as specified in IA32 manuals:
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;
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; +---------------------+ <-- 16-byte aligned ensured by processor
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; + Old SS +
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; +---------------------+
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; + Old RSP +
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; +---------------------+
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; + RFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + RIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + Vector Number +
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; +---------------------+
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; + RBP +
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; +---------------------+ <-- RBP, 16-byte aligned
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;
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; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
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;------------------------------------------------------------------------------
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global ASM_PFX(PageFaultIdtHandlerSmmProfile)
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ASM_PFX(PageFaultIdtHandlerSmmProfile):
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push 0xe ; Page Fault
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test spl, 8 ; odd multiple of 8 => ErrCode present
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jnz .0
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push qword [rsp] ; duplicate INT# if no ErrCode
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mov qword [rsp + 8], 0
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.0:
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push rbp
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mov rbp, rsp
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;
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; Since here the stack pointer is 16-byte aligned, so
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; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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; is 16-byte aligned
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;
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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push r15
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push r14
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push r13
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push r12
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push r11
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push r10
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push r9
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push r8
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push rax
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push rcx
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push rdx
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push rbx
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push qword [rbp + 48] ; RSP
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push qword [rbp] ; RBP
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push rsi
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push rdi
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzx rax, word [rbp + 56]
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push rax ; for ss
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movzx rax, word [rbp + 32]
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push rax ; for cs
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mov rax, ds
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push rax
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mov rax, es
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push rax
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mov rax, fs
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push rax
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mov rax, gs
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push rax
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;; UINT64 Rip;
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push qword [rbp + 24]
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;; UINT64 Gdtr[2], Idtr[2];
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sub rsp, 16
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sidt [rsp]
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sub rsp, 16
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sgdt [rsp]
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;; UINT64 Ldtr, Tr;
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xor rax, rax
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str ax
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push rax
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sldt ax
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push rax
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;; UINT64 RFlags;
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push qword [rbp + 40]
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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mov rax, cr8
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push rax
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mov rax, cr4
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or rax, 0x208
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mov cr4, rax
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push rax
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mov rax, cr3
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push rax
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mov rax, cr2
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push rax
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xor rax, rax
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push rax
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mov rax, cr0
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push rax
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov rax, dr7
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push rax
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mov rax, dr6
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push rax
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mov rax, dr3
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push rax
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mov rax, dr2
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push rax
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mov rax, dr1
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push rax
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mov rax, dr0
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push rax
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;; FX_SAVE_STATE_X64 FxSaveState;
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sub rsp, 512
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mov rdi, rsp
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db 0xf, 0xae, 00000111y ;fxsave [rdi]
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; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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cld
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;; UINT32 ExceptionData;
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push qword [rbp + 16]
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;; call into exception handler
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mov rcx, [rbp + 8]
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lea rax, [ASM_PFX(SmiPFHandler)]
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;; Prepare parameter and call
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mov rdx, rsp
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;
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; Per X64 calling convention, allocate maximum parameter stack space
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; and make sure RSP is 16-byte aligned
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;
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sub rsp, 4 * 8 + 8
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call rax
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add rsp, 4 * 8 + 8
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jmp .1
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.1:
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;; UINT64 ExceptionData;
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add rsp, 8
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;; FX_SAVE_STATE_X64 FxSaveState;
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mov rsi, rsp
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db 0xf, 0xae, 00001110y ; fxrstor [rsi]
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add rsp, 512
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; Skip restoration of DRx registers to support debuggers
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;; that set breakpoints in interrupt/exception context
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add rsp, 8 * 6
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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pop rax
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mov cr0, rax
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add rsp, 8 ; not for Cr1
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pop rax
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mov cr2, rax
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pop rax
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mov cr3, rax
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pop rax
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mov cr4, rax
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pop rax
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mov cr8, rax
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;; UINT64 RFlags;
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pop qword [rbp + 40]
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;; UINT64 Ldtr, Tr;
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;; UINT64 Gdtr[2], Idtr[2];
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;; Best not let anyone mess with these particular registers...
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add rsp, 48
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;; UINT64 Rip;
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pop qword [rbp + 24]
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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pop rax
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; mov gs, rax ; not for gs
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pop rax
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; mov fs, rax ; not for fs
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; (X64 will not use fs and gs, so we do not restore it)
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pop rax
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mov es, rax
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pop rax
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mov ds, rax
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pop qword [rbp + 32] ; for cs
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pop qword [rbp + 56] ; for ss
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pop rdi
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pop rsi
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add rsp, 8 ; not for rbp
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pop qword [rbp + 48] ; for rsp
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pop rbx
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pop rdx
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pop rcx
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pop rax
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pop r8
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pop r9
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pop r10
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pop r11
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pop r12
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pop r13
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pop r14
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pop r15
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mov rsp, rbp
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; Enable TF bit after page fault handler runs
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bts dword [rsp + 40], 8 ;RFLAGS
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pop rbp
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add rsp, 16 ; skip INT# & ErrCode
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iretq
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