ce6aec3ea3
In SVN 18756 ("disallow whole D-cache maintenance operations")
InvalidateInstructionCache was modified to remove the full data cache
clean but left the full instruction cache invalidate. The change was
made to address issues in the set/way clean methodology but the
resulting code could lead someone to a painful debug. If a component
called this function, the proper code would not be flushed to the PoU,
since the intent of this function is not only to invalidate the I-cache
but to provide coherency after code loading / modification. This change
simply places an ASSERT(FALSE) in this function to avoid this hazard.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19084 6f19259b-4bc3-4df7-8a09-765794883524
122 lines
2.6 KiB
C
122 lines
2.6 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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VOID
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CacheRangeOperation (
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IN VOID *Start,
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IN UINTN Length,
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IN LINE_OPERATION LineOperation
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)
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{
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UINTN ArmCacheLineLength = ArmDataCacheLineLength();
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UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
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// Align address (rounding down)
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UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
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UINTN EndAddress = (UINTN)Start + Length;
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// Perform the line operation on an address in each cache line
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while (AlignedAddress < EndAddress) {
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LineOperation(AlignedAddress);
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AlignedAddress += ArmCacheLineLength;
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}
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ArmDataSynchronizationBarrier ();
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}
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VOID
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EFIAPI
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InvalidateInstructionCache (
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VOID
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)
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{
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ASSERT (FALSE);
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}
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VOID
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EFIAPI
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InvalidateDataCache (
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VOID
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)
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{
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ASSERT (FALSE);
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}
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VOID *
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EFIAPI
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InvalidateInstructionCacheRange (
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IN VOID *Address,
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IN UINTN Length
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)
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{
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CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);
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ArmInvalidateInstructionCache ();
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return Address;
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}
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VOID
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EFIAPI
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WriteBackInvalidateDataCache (
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VOID
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)
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{
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ASSERT (FALSE);
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}
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VOID *
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EFIAPI
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WriteBackInvalidateDataCacheRange (
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IN VOID *Address,
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IN UINTN Length
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)
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{
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CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA);
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return Address;
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}
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VOID
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EFIAPI
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WriteBackDataCache (
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VOID
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)
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{
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ASSERT (FALSE);
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}
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VOID *
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EFIAPI
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WriteBackDataCacheRange (
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IN VOID *Address,
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IN UINTN Length
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)
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{
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CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA);
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return Address;
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}
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VOID *
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EFIAPI
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InvalidateDataCacheRange (
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IN VOID *Address,
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IN UINTN Length
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)
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{
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CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA);
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return Address;
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}
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