83886d746e
The PrePeiCore vector table for AArch64 mode is only half populated.
However unlikely, if exceptions from lower exception levels are ever
taken, they should be reported correctly, rather than causing a
recursive undefined instruction fault on the zero padding that was
introduced by commit SVN r18904 ("ArmPkg/ArmPlatformPkg: position
vectors relative to base"). So add the missing entries, and wire
them up to the default handler.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18976 6f19259b-4bc3-4df7-8a09-765794883524
121 lines
3.4 KiB
ArmAsm
121 lines
3.4 KiB
ArmAsm
#
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# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#
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#include <Chipset/AArch64.h>
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#include <AsmMacroIoLibV8.h>
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#include <Base.h>
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#include <AutoGen.h>
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.text
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//============================================================
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//Default Exception Handlers
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//============================================================
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#define TO_HANDLER \
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EL1_OR_EL2(x1) \
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1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\
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b 3f ;\
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2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\
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3: bl ASM_PFX(PeiCommonExceptionEntry) ;
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//
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// Default Exception handlers: There is no plan to return from any of these exceptions.
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// No context saving at all.
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//
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VECTOR_BASE(PeiVectorTable)
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)
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_DefaultSyncExceptHandler_t:
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)
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_DefaultIrq_t:
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mov x0, #EXCEPT_AARCH64_IRQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)
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_DefaultFiq_t:
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mov x0, #EXCEPT_AARCH64_FIQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)
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_DefaultSError_t:
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mov x0, #EXCEPT_AARCH64_SERROR
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)
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_DefaultSyncExceptHandler_h:
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)
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_DefaultIrq_h:
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mov x0, #EXCEPT_AARCH64_IRQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)
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_DefaultFiq_h:
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mov x0, #EXCEPT_AARCH64_FIQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)
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_DefaultSError_h:
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mov x0, #EXCEPT_AARCH64_SERROR
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)
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_DefaultSyncExceptHandler_LowerA64:
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)
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_DefaultIrq_LowerA64:
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mov x0, #EXCEPT_AARCH64_IRQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)
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_DefaultFiq_LowerA64:
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mov x0, #EXCEPT_AARCH64_FIQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)
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_DefaultSError_LowerA64:
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mov x0, #EXCEPT_AARCH64_SERROR
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)
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_DefaultSyncExceptHandler_LowerA32:
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)
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_DefaultIrq_LowerA32:
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mov x0, #EXCEPT_AARCH64_IRQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)
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_DefaultFiq_LowerA32:
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mov x0, #EXCEPT_AARCH64_FIQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)
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_DefaultSError_LowerA32:
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mov x0, #EXCEPT_AARCH64_SERROR
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TO_HANDLER
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VECTOR_END(PeiVectorTable)
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