5458faf845
The AArch64 DAIF bits are different for reading (mrs) versus writing (msr). The bitmask definitions assumed they were the same causing incorrect results when trying to determine the current interrupt state through GetInterruptState. The logic for interpreting the DAIF read data using the csel instruction was also incorrect and is fixed. Replaced the magic numbers in DisableInterrupts.S and EnableInterrupts.S with definitions for the DAIF write (daifset/daifclr) IRQ field. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
37 lines
1.1 KiB
ArmAsm
37 lines
1.1 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# DisableInterrupts() for AArch64
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#
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# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 2
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GCC_ASM_EXPORT(DisableInterrupts)
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.set DAIF_WR_IRQ_BIT, (1 << 1)
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#/**
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# Disables CPU interrupts.
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#
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#**/
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#VOID
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#EFIAPI
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#DisableInterrupts (
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# VOID
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# );
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#
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ASM_PFX(DisableInterrupts):
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msr daifset, #DAIF_WR_IRQ_BIT
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ret
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