6f7878a972
The value of EBX must be preserved to follow IA32 cdecl calling convention in the assembly implementation of AsmFlushCacheLine(). The CPUID instruction modifies the EBX register. The EBX register value is saved onto the stack before CPUID and restored from the stack after CPUID. The update to the inline assembly implementation of AsmFlushCacheLine() changed the location of the LinearAddress parameter value on the stack. The hardcoded lookup using [esp + 4] is not correct. Use the parameter name LinearAddress instead of the hard coded [esp + 4] stack location to prevent this issue from occurring again if there are changes to the inline assembly in the future. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17279 6f19259b-4bc3-4df7-8a09-765794883524
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/** @file
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AsmFlushCacheLine function
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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/**
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Flushes a cache line from all the instruction and data caches within the
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coherency domain of the CPU.
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Flushed the cache line specified by LinearAddress, and returns LinearAddress.
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This function is only available on IA-32 and x64.
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@param LinearAddress The address of the cache line to flush. If the CPU is
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in a physical addressing mode, then LinearAddress is a
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physical address. If the CPU is in a virtual
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addressing mode, then LinearAddress is a virtual
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address.
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@return LinearAddress
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**/
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VOID *
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EFIAPI
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AsmFlushCacheLine (
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IN VOID *LinearAddress
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)
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{
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//
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// If the CPU does not support CLFLUSH instruction,
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// then promote flush range to flush entire cache.
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//
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_asm {
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mov eax, 1
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cpuid
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test edx, BIT19
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jz NoClflush
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mov eax, dword ptr [LinearAddress]
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clflush [eax]
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jmp Done
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NoClflush:
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wbinvd
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Done:
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}
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return LinearAddress;
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}
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