209b8f3c27
The base address for the interrupt controller is hard-coded in Omap3530Interrupt.h, although Omap35xxPkg/InterruptDxe appears to have initially intended to make use of PcdInterruptBaseAddress from EmbeddedPkg. Move it to use said Pcd, and also declare use of it in BeagleBoardLib, which makes a direct access. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
52 lines
2.2 KiB
C
52 lines
2.2 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OMAP3530INTERRUPT_H__
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#define __OMAP3530INTERRUPT_H__
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#include <Library/PcdLib.h>
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#define INTERRUPT_BASE (PcdGet32 (PcdInterruptBaseAddress))
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#define INT_NROF_VECTORS (96)
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#define MAX_VECTOR (INT_NROF_VECTORS - 1)
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#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)
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#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)
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#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)
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#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)
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#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)
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#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)
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#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)
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#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)
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#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)
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#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)
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#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))
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#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))
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#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))
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#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))
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#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))
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#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))
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#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))
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#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
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#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
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#define INTCPS_ILR_FIQ BIT0
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#define INTCPS_SIR_IRQ_MASK (0x7F)
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#define INTCPS_CONTROL_NEWIRQAGR BIT0
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#define INTCPS_CONTROL_NEWFIQAGR BIT1
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#endif // __OMAP3530INTERRUPT_H__
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