40f849aac5
Problems have been encountered because some of the source files have execute permission set. This can cause git to report them as changed when they are checked out onto a file system with inherited permissions. This has been seen using Cygwin, MinGW and PowerShell Git. This patch makes no change to source file content, and only aims to correct the file modes/permissions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19790 6f19259b-4bc3-4df7-8a09-765794883524
166 lines
3.8 KiB
C
166 lines
3.8 KiB
C
/** @file
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Debug Agent timer lib for OMAP 35xx.
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include <Library/OmapLib.h>
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#include <Library/ArmLib.h>
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#include <Library/PcdLib.h>
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#include <Omap3530/Omap3530.h>
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volatile UINT32 gVector;
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// Cached registers
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volatile UINT32 gTISR;
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volatile UINT32 gTCLR;
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volatile UINT32 gTLDR;
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volatile UINT32 gTCRR;
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volatile UINT32 gTIER;
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VOID
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EnableInterruptSource (
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VOID
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)
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{
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UINTN Bank;
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UINTN Bit;
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// Map vector to FIQ, IRQ is default
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MmioWrite32 (INTCPS_ILR (gVector), 1);
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Bank = gVector / 32;
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Bit = 1UL << (gVector % 32);
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MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
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}
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VOID
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DisableInterruptSource (
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VOID
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)
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{
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UINTN Bank;
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UINTN Bit;
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Bank = gVector / 32;
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Bit = 1UL << (gVector % 32);
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MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
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}
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/**
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Setup all the hardware needed for the debug agents timer.
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This function is used to set up debug enviroment. It may enable interrupts.
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**/
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VOID
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EFIAPI
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DebugAgentTimerIntialize (
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VOID
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)
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{
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UINT32 TimerBaseAddress;
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UINT32 TimerNumber;
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TimerNumber = PcdGet32(PcdOmap35xxDebugAgentTimer);
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gVector = InterruptVectorForTimer (TimerNumber);
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// Set up the timer registers
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TimerBaseAddress = TimerBase (TimerNumber);
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gTISR = TimerBaseAddress + GPTIMER_TISR;
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gTCLR = TimerBaseAddress + GPTIMER_TCLR;
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gTLDR = TimerBaseAddress + GPTIMER_TLDR;
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gTCRR = TimerBaseAddress + GPTIMER_TCRR;
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gTIER = TimerBaseAddress + GPTIMER_TIER;
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if ((TimerNumber < 2) || (TimerNumber > 9)) {
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// This code assumes one the General Purpose timers is used
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// GPT2 - GPT9
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CpuDeadLoop ();
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}
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// Set source clock for GPT2 - GPT9 to SYS_CLK
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MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2));
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}
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/**
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Set the period for the debug agent timer. Zero means disable the timer.
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@param[in] TimerPeriodMilliseconds Frequency of the debug agent timer.
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**/
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VOID
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EFIAPI
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DebugAgentTimerSetPeriod (
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IN UINT32 TimerPeriodMilliseconds
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)
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{
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UINT64 TimerCount;
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INT32 LoadValue;
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if (TimerPeriodMilliseconds == 0) {
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// Turn off GPTIMER3
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MmioWrite32 (gTCLR, TCLR_ST_OFF);
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DisableInterruptSource ();
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} else {
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// Calculate required timer count
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TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds));
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// Set GPTIMER5 Load register
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LoadValue = (INT32) -TimerCount;
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MmioWrite32 (gTLDR, LoadValue);
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MmioWrite32 (gTCRR, LoadValue);
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// Enable Overflow interrupt
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MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
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// Turn on GPTIMER3, it will reload at overflow
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MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
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EnableInterruptSource ();
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}
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}
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/**
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Perform End Of Interrupt for the debug agent timer. This is called in the
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interrupt handler after the interrupt has been processed.
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**/
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VOID
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EFIAPI
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DebugAgentTimerEndOfInterrupt (
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VOID
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)
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{
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// Clear all timer interrupts
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MmioWrite32 (gTISR, TISR_CLEAR_ALL);
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// Poll interrupt status bits to ensure clearing
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while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
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MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);
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ArmDataSynchronizationBarrier ();
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}
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