b303605e1b
Changes for V4 ============== 1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode from QuarkPlatformPkg commit to QuarkSocPkg commit 2) Fix incorrect license header in PlatformSecLibModStrs.uni Changes for V3 ============== 1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc This is required because QuarkMin.dsc uses the emulated variable driver that does not preserve any non-volatile UEFI variables across reset. If the condition is met where the memory type information variable needs to be updated, then the system will reset every time the UEFI Shell is run. By setting this PCD to FALSE, then reset action is disabled. 2) Move one binary file to QuarkSocBinPkg 3) Change RMU.bin FILE statements to INF statement in DSC FD region to be compatible with PACKAGES_PATH search for QuarkSocBinPkg Changes for V2 ============== 1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg 2) Configure PcdPciSerialParameters for PCI serial driver for Quark 3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM 4) Convert all UNI files to utf-8 5) Replace tabs with spaces and remove trailing spaces 6) Add License.txt Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Acked-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
147 lines
4.3 KiB
C
147 lines
4.3 KiB
C
/** @file
|
|
Do platform initialization for PCI bridge.
|
|
|
|
Copyright (c) 2013-2015 Intel Corporation.
|
|
|
|
This program and the accompanying materials
|
|
are licensed and made available under the terms and conditions of the BSD License
|
|
which accompanies this distribution. The full text of the license may be found at
|
|
http://opensource.org/licenses/bsd-license.php
|
|
|
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
|
|
|
|
**/
|
|
|
|
#include "PciHostBridge.h"
|
|
|
|
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
|
|
|
|
EFI_STATUS
|
|
ChipsetPreprocessController (
|
|
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
|
|
IN EFI_HANDLE RootBridgeHandle,
|
|
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
|
|
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
This function is called for all the PCI controllers that the PCI
|
|
bus driver finds. Can be used to Preprogram the controller.
|
|
|
|
Arguments:
|
|
This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
|
|
RootBridgeHandle -- The PCI Root Bridge handle
|
|
PciBusAddress -- Address of the controller on the PCI bus
|
|
Phase -- The Phase during resource allocation
|
|
|
|
Returns:
|
|
EFI_SUCCESS
|
|
|
|
--*/
|
|
|
|
// GC_TODO: PciAddress - add argument and description to function comment
|
|
//
|
|
// GC_TODO: PciAddress - add argument and description to function comment
|
|
//
|
|
// GC_TODO: PciAddress - add argument and description to function comment
|
|
//
|
|
// GC_TODO: PciAddress - add argument and description to function comment
|
|
//
|
|
{
|
|
|
|
EFI_STATUS Status;
|
|
UINT8 Latency;
|
|
UINT8 CacheLineSize;
|
|
|
|
if (mPciRootBridgeIo == NULL) {
|
|
//
|
|
// Get root bridge in the system.
|
|
//
|
|
Status = gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIoProtocolGuid, (VOID **) &mPciRootBridgeIo);
|
|
ASSERT_EFI_ERROR (Status);
|
|
}
|
|
|
|
if (Phase == EfiPciBeforeResourceCollection) {
|
|
//
|
|
// Program the latency register, CLS register
|
|
//
|
|
PciAddress.Register = PCI_LATENCY_TIMER_OFFSET;
|
|
mPciRootBridgeIo->Pci.Read (
|
|
mPciRootBridgeIo,
|
|
EfiPciWidthUint8,
|
|
*((UINT64 *) &PciAddress),
|
|
1,
|
|
&Latency
|
|
);
|
|
|
|
//
|
|
// PCI-x cards come up with a default latency of 0x40. Don't touch them.
|
|
//
|
|
if (Latency == 0) {
|
|
Latency = DEFAULT_PCI_LATENCY;
|
|
mPciRootBridgeIo->Pci.Write (
|
|
mPciRootBridgeIo,
|
|
EfiPciWidthUint8,
|
|
*((UINT64 *) &PciAddress),
|
|
1,
|
|
&Latency
|
|
);
|
|
}
|
|
//
|
|
// Program Cache Line Size as 64bytes
|
|
// 16 of DWORDs = 64bytes (0x10)
|
|
//
|
|
PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET;
|
|
CacheLineSize = 0x10;
|
|
mPciRootBridgeIo->Pci.Write (
|
|
mPciRootBridgeIo,
|
|
EfiPciWidthUint8,
|
|
*((UINT64 *) &PciAddress),
|
|
1,
|
|
&CacheLineSize
|
|
);
|
|
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
UINT64
|
|
GetAllocAttributes (
|
|
IN UINTN RootBridgeIndex
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Returns the Allocation attributes for the BNB Root Bridge.
|
|
|
|
Arguments:
|
|
|
|
RootBridgeIndex - The root bridge number. 0 based.
|
|
|
|
Returns:
|
|
|
|
EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE
|
|
|
|
--*/
|
|
{
|
|
//
|
|
// Cannot have more than one Root bridge
|
|
//
|
|
//ASSERT (RootBridgeIndex == 0);
|
|
|
|
//
|
|
// PCI Root Bridge does not support separate windows for Non-prefetchable
|
|
// and Prefetchable memory. A PCI bus driver needs to include requests for
|
|
// Prefetchable memory in the Non-prefetchable memory pool.
|
|
// Further TNB does not support 64 bit memory apertures for PCI. BNB
|
|
// can only have system memory above 4 GB,
|
|
//
|
|
|
|
return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
|
|
}
|