09119a00cc
Add a new instances of the SmmCpuFeaturesLib that is used by platforms to enable the SMI Transfer Monitor(STM) feature. This new instance is in the same directory as the default SmmCpuFeaturesLib instance in order to share source files. The DSC file is updated to build both SmmCpuFeatureLib instances and to build two versions of the PiSmmCpuDxeSmm module using each of the SmmCpuFeatureLib instances. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
283 lines
8.0 KiB
ArmAsm
283 lines
8.0 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# SmiEntry.S
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#
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# Abstract:
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#
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# Code template of the SMI handler for a particular processor
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(gcStmSmiHandlerTemplate)
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ASM_GLOBAL ASM_PFX(gcStmSmiHandlerSize)
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ASM_GLOBAL ASM_PFX(gcStmSmiHandlerOffset)
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ASM_GLOBAL ASM_PFX(gStmSmiCr3)
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ASM_GLOBAL ASM_PFX(gStmSmiStack)
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ASM_GLOBAL ASM_PFX(gStmSmbase)
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ASM_GLOBAL ASM_PFX(gStmXdSupported)
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ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
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.equ MSR_IA32_MISC_ENABLE, 0x1A0
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.equ MSR_EFER, 0xc0000080
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.equ MSR_EFER_XD, 0x800
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#
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# Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
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#
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.equ DSC_OFFSET, 0xfb00
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.equ DSC_GDTPTR, 0x48
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.equ DSC_GDTSIZ, 0x50
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.equ DSC_CS, 0x14
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.equ DSC_DS, 0x16
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.equ DSC_SS, 0x18
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.equ DSC_OTHERSEG, 0x1a
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#
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# Constants relating to CPU State Save Area
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#
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.equ SSM_DR6, 0xffd0
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.equ SSM_DR7, 0xffc8
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.equ PROTECT_MODE_CS, 0x08
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.equ PROTECT_MODE_DS, 0x20
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.equ LONG_MODE_CS, 0x38
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.equ TSS_SEGMENT, 0x40
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.equ GDT_SIZE, 0x50
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.text
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ASM_PFX(gcStmSmiHandlerTemplate):
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_StmSmiEntryPoint:
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#
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# The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
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# bit addressing mode. And that coincidence has been used in the following
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# "64-bit like" 16-bit code. Be aware that once RDI is referenced as a
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# base address register, it is actually BX that is referenced.
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#
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.byte 0xbb # mov bx, imm16
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.word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
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#
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# fix GDT descriptor
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#
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.byte 0x2e,0xa1 # mov ax, cs:[offset16]
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.word DSC_OFFSET + DSC_GDTSIZ
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.byte 0x48 # dec ax
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.byte 0x2e
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movl %eax, (%rdi) # mov cs:[bx], ax
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.byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
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.word DSC_OFFSET + DSC_GDTPTR
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.byte 0x2e
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movw %ax, 2(%rdi)
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.byte 0x66,0x2e
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lgdt (%rdi)
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#
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# Patch ProtectedMode Segment
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#
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.byte 0xb8
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.word PROTECT_MODE_CS
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.byte 0x2e
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movl %eax, -2(%rdi)
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#
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# Patch ProtectedMode entry
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#
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.byte 0x66, 0xbf # mov edi, SMBASE
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ASM_PFX(gStmSmbase): .space 4
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lea ((ProtectedMode - _StmSmiEntryPoint) + 0x8000)(%edi), %ax
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.byte 0x2e
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movw %ax, -6(%rdi)
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#
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# Switch into ProtectedMode
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#
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movq %cr0, %rbx
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.byte 0x66
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andl $0x9ffafff3, %ebx
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.byte 0x66
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orl $0x00000023, %ebx
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movq %rbx, %cr0
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.byte 0x66, 0xea
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.space 6
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_StmGdtDesc: .space 6
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ProtectedMode:
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movw $PROTECT_MODE_DS, %ax
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movl %eax, %ds
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movl %eax, %es
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movl %eax, %fs
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movl %eax, %gs
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movl %eax, %ss
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.byte 0xbc # mov esp, imm32
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ASM_PFX(gStmSmiStack): .space 4
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jmp ProtFlatMode
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ProtFlatMode:
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.byte 0xb8
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ASM_PFX(gStmSmiCr3): .space 4
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movq %rax, %cr3
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movl $0x668,%eax # as cr4.PGE is not set here, refresh cr3
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movq %rax, %cr4 # in PreModifyMtrrs() to flush TLB.
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# Load TSS
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subl $8, %esp # reserve room in stack
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sgdt (%rsp)
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movl 2(%rsp), %eax # eax = GDT base
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addl $8, %esp
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movb $0x89, %dl
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movb %dl, (TSS_SEGMENT + 5)(%rax) # clear busy flag
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movl $TSS_SEGMENT, %eax
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ltr %ax
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# enable NXE if supported
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.byte 0xb0 # mov al, imm8
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ASM_PFX(gStmXdSupported): .byte 1
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cmpb $0, %al
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jz SkipXd
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#
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# Check XD disable bit
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#
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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subl $4, %esp
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pushq %rdx # save MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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jz L13
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andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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wrmsr
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L13:
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movl $MSR_EFER, %ecx
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rdmsr
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orw $MSR_EFER_XD,%ax # enable NXE
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wrmsr
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jmp XdDone
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SkipXd:
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subl $8, %esp
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XdDone:
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#
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# Switch to LongMode
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#
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pushq $LONG_MODE_CS # push cs hardcore here
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call Base # push return address for retf later
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Base:
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addl $(LongMode - Base), (%rsp) # offset for far retf, seg is the 1st arg
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movl $MSR_EFER, %ecx
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rdmsr
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orb $1,%ah # enable LME
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wrmsr
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movq %cr0, %rbx
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orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
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movq %rbx, %cr0
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retf
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LongMode: # long mode (64-bit code) starts here
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movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
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lidt (%rax)
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lea (DSC_OFFSET)(%rdi), %ebx
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movw DSC_DS(%rbx), %ax
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movl %eax,%ds
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movw DSC_OTHERSEG(%rbx), %ax
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movl %eax,%es
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movl %eax,%fs
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movl %eax,%gs
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movw DSC_SS(%rbx), %ax
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movl %eax,%ss
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CommonHandler:
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movq 8(%rsp), %rbx
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# Save FP registers
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subq $0x200, %rsp
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.byte 0x48 # FXSAVE64
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fxsave (%rsp)
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addq $-0x20, %rsp
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movq %rbx, %rcx
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movabsq $ASM_PFX(CpuSmmDebugEntry), %rax
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call *%rax
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movq %rbx, %rcx
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movabsq $ASM_PFX(SmiRendezvous), %rax
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call *%rax
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movq %rbx, %rcx
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movabsq $ASM_PFX(CpuSmmDebugExit), %rax
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call *%rax
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addq $0x20, %rsp
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#
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# Restore FP registers
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#
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.byte 0x48 # FXRSTOR64
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fxrstor (%rsp)
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addq $0x200, %rsp
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movabsq $ASM_PFX(gStmXdSupported), %rax
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movb (%rax), %al
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cmpb $0, %al
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jz L16
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popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx
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jz L16
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
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wrmsr
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L16:
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rsm
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_StmSmiHandler:
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#
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# Check XD disable bit
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#
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xorq %r8, %r8
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movabsq $ASM_PFX(gStmXdSupported), %rax
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movb (%rax), %al
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cmpb $0, %al
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jz StmXdDone
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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jz L14
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andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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wrmsr
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L14:
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movl $MSR_EFER, %ecx
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rdmsr
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orw $MSR_EFER_XD,%ax # enable NXE
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wrmsr
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StmXdDone:
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pushq %r8
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# below step is needed, because STM does not run above code.
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# we have to run below code to set IDT/CR0/CR4
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movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
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lidt (%rax)
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movq %cr0, %rax
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orl $0x80010023, %eax
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movq %rax, %cr0
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movq %cr4, %rax
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movl $0x668, %eax # as cr4.PGE is not set here, refresh cr3
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movq %rax, %cr4 # in PreModifyMtrrs() to flush TLB.
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# STM init finish
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jmp CommonHandler
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ASM_PFX(gcStmSmiHandlerSize) : .word . - _StmSmiEntryPoint
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ASM_PFX(gcStmSmiHandlerOffset): .word _StmSmiHandler - _StmSmiEntryPoint
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