09119a00cc
Add a new instances of the SmmCpuFeaturesLib that is used by platforms to enable the SMI Transfer Monitor(STM) feature. This new instance is in the same directory as the default SmmCpuFeaturesLib instance in order to share source files. The DSC file is updated to build both SmmCpuFeatureLib instances and to build two versions of the PiSmmCpuDxeSmm module using each of the SmmCpuFeatureLib instances. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
282 lines
8.2 KiB
NASM
282 lines
8.2 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiEntry.asm
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;
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; Abstract:
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;
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; Code template of the SMI handler for a particular processor
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;
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;-------------------------------------------------------------------------------
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;
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; Variables referenced by C code
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;
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EXTERNDEF SmiRendezvous:PROC
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EXTERNDEF CpuSmmDebugEntry:PROC
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EXTERNDEF CpuSmmDebugExit:PROC
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EXTERNDEF gcStmSmiHandlerTemplate:BYTE
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EXTERNDEF gcStmSmiHandlerSize:WORD
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EXTERNDEF gcStmSmiHandlerOffset:WORD
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EXTERNDEF gStmSmiCr3:DWORD
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EXTERNDEF gStmSmiStack:DWORD
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EXTERNDEF gStmSmbase:DWORD
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EXTERNDEF gStmXdSupported:BYTE
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EXTERNDEF gStmSmiHandlerIdtr:FWORD
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MSR_IA32_MISC_ENABLE EQU 1A0h
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MSR_EFER EQU 0c0000080h
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MSR_EFER_XD EQU 0800h
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;
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; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
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;
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DSC_OFFSET EQU 0fb00h
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DSC_GDTPTR EQU 48h
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DSC_GDTSIZ EQU 50h
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DSC_CS EQU 14h
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DSC_DS EQU 16h
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DSC_SS EQU 18h
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DSC_OTHERSEG EQU 1ah
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;
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; Constants relating to CPU State Save Area
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;
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SSM_DR6 EQU 0ffd0h
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SSM_DR7 EQU 0ffc8h
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PROTECT_MODE_CS EQU 08h
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PROTECT_MODE_DS EQU 20h
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LONG_MODE_CS EQU 38h
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TSS_SEGMENT EQU 40h
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GDT_SIZE EQU 50h
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.code
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gcStmSmiHandlerTemplate LABEL BYTE
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_StmSmiEntryPoint:
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;
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; The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
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; bit addressing mode. And that coincidence has been used in the following
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; "64-bit like" 16-bit code. Be aware that once RDI is referenced as a
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; base address register, it is actually BX that is referenced.
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;
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DB 0bbh ; mov bx, imm16
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DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc offset
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; fix GDT descriptor
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DB 2eh, 0a1h ; mov ax, cs:[offset16]
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DW DSC_OFFSET + DSC_GDTSIZ
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DB 48h ; dec ax
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DB 2eh
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mov [rdi], eax ; mov cs:[bx], ax
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DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
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DW DSC_OFFSET + DSC_GDTPTR
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DB 2eh
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mov [rdi + 2], ax ; mov cs:[bx + 2], eax
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DB 66h, 2eh
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lgdt fword ptr [rdi] ; lgdt fword ptr cs:[bx]
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; Patch ProtectedMode Segment
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DB 0b8h ; mov ax, imm16
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DW PROTECT_MODE_CS ; set AX for segment directly
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DB 2eh
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mov [rdi - 2], eax ; mov cs:[bx - 2], ax
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; Patch ProtectedMode entry
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DB 66h, 0bfh ; mov edi, SMBASE
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gStmSmbase DD ?
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lea ax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 8000h]
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DB 2eh
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mov [rdi - 6], ax ; mov cs:[bx - 6], eax
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; Switch into @ProtectedMode
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mov rbx, cr0
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DB 66h
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and ebx, 9ffafff3h
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DB 66h
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or ebx, 00000023h
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mov cr0, rbx
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DB 66h, 0eah
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DD ?
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DW ?
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_StmGdtDesc FWORD ?
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@ProtectedMode:
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mov ax, PROTECT_MODE_DS
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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DB 0bch ; mov esp, imm32
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gStmSmiStack DD ?
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jmp ProtFlatMode
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ProtFlatMode:
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DB 0b8h ; mov eax, offset gStmSmiCr3
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gStmSmiCr3 DD ?
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mov cr3, rax
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mov eax, 668h ; as cr4.PGE is not set here, refresh cr3
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mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
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; Load TSS
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sub esp, 8 ; reserve room in stack
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sgdt fword ptr [rsp]
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mov eax, [rsp + 2] ; eax = GDT base
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add esp, 8
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mov dl, 89h
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mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag
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mov eax, TSS_SEGMENT
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ltr ax
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; enable NXE if supported
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DB 0b0h ; mov al, imm8
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gStmXdSupported DB 1
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cmp al, 0
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jz @SkipXd
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;
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; Check XD disable bit
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;
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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sub esp, 4
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push rdx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz @f
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and dx, 0FFFBh ; clear XD Disable bit if it is set
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wrmsr
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@@:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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jmp @XdDone
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@SkipXd:
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sub esp, 8
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@XdDone:
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; Switch into @LongMode
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push LONG_MODE_CS ; push cs hardcore here
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call Base ; push return address for retf later
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Base:
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add dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg
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mov ecx, MSR_EFER
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rdmsr
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or ah, 1 ; enable LME
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wrmsr
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mov rbx, cr0
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or ebx, 080010023h ; enable paging + WP + NE + MP + PE
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mov cr0, rbx
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retf
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@LongMode: ; long mode (64-bit code) starts here
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mov rax, offset gStmSmiHandlerIdtr
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lidt fword ptr [rax]
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lea ebx, [rdi + DSC_OFFSET]
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mov ax, [rbx + DSC_DS]
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mov ds, eax
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mov ax, [rbx + DSC_OTHERSEG]
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mov es, eax
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mov fs, eax
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mov gs, eax
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mov ax, [rbx + DSC_SS]
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mov ss, eax
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CommonHandler:
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mov rbx, [rsp + 0x08] ; rbx <- CpuIndex
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;
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; Save FP registers
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;
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sub rsp, 200h
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DB 48h ; FXSAVE64
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fxsave [rsp]
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add rsp, -20h
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mov rcx, rbx
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mov rax, CpuSmmDebugEntry
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call rax
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mov rcx, rbx
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mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous
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call rax
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mov rcx, rbx
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mov rax, CpuSmmDebugExit
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call rax
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add rsp, 20h
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;
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; Restore FP registers
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;
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DB 48h ; FXRSTOR64
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fxrstor [rsp]
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add rsp, 200h
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mov rax, offset ASM_PFX(gStmXdSupported)
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mov al, [rax]
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cmp al, 0
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jz @f
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pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz @f
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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@@:
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rsm
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_StmSmiHandler:
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;
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; Check XD disable bit
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;
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xor r8, r8
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mov rax, offset ASM_PFX(gStmXdSupported)
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mov al, [rax]
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cmp al, 0
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jz @StmXdDone
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz @f
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and dx, 0FFFBh ; clear XD Disable bit if it is set
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wrmsr
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@@:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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@StmXdDone:
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push r8
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; below step is needed, because STM does not run above code.
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; we have to run below code to set IDT/CR0/CR4
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mov rax, offset gStmSmiHandlerIdtr
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lidt fword ptr [rax]
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mov rax, cr0
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or eax, 80010023h ; enable paging + WP + NE + MP + PE
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mov cr0, rax
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mov rax, cr4
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mov eax, 668h ; as cr4.PGE is not set here, refresh cr3
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mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
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; STM init finish
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jmp CommonHandler
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gcStmSmiHandlerSize DW $ - _StmSmiEntryPoint
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gcStmSmiHandlerOffset DW _StmSmiHandler - _StmSmiEntryPoint
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END
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