09119a00cc
Add a new instances of the SmmCpuFeaturesLib that is used by platforms to enable the SMI Transfer Monitor(STM) feature. This new instance is in the same directory as the default SmmCpuFeaturesLib instance in order to share source files. The DSC file is updated to build both SmmCpuFeatureLib instances and to build two versions of the PiSmmCpuDxeSmm module using each of the SmmCpuFeatureLib instances. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
/** @file
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SMM STM support functions
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Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiSmm.h>
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#include <Library/DebugLib.h>
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#include "SmmStm.h"
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///
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/// Page Table Entry
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///
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define IA32_PG_PS BIT7
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/**
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Create 4G page table for STM.
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2M PAE page table in X64 version.
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@param PageTableBase The page table base in MSEG
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**/
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VOID
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StmGen4GPageTable (
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IN UINTN PageTableBase
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)
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{
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UINTN Index;
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UINTN SubIndex;
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UINT64 *Pde;
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UINT64 *Pte;
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UINT64 *Pml4;
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Pml4 = (UINT64*)(UINTN)PageTableBase;
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PageTableBase += SIZE_4KB;
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*Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;
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Pde = (UINT64*)(UINTN)PageTableBase;
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PageTableBase += SIZE_4KB;
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Pte = (UINT64 *)(UINTN)PageTableBase;
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for (Index = 0; Index < 4; Index++) {
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*Pde = PageTableBase | IA32_PG_RW | IA32_PG_P;
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Pde++;
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PageTableBase += SIZE_4KB;
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for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof (*Pte); SubIndex++) {
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*Pte = (((Index << 9) + SubIndex) << 21) | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
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Pte++;
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}
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}
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}
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/**
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This is SMM exception handle.
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Consumed by STM when exception happen.
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@param Context STM protection exception stack frame
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@return the EBX value for STM reference.
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EBX = 0: resume SMM guest using register state found on exception stack.
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EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the
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TXT.ERRORCODE register and subsequently reset the system via
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TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as
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follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
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EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.
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**/
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UINT32
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EFIAPI
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SmmStmExceptionHandler (
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IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
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)
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{
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// TBD - SmmStmExceptionHandler, record information
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DEBUG ((DEBUG_ERROR, "SmmStmExceptionHandler ...\n"));
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//
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// Skip this instruction and continue;
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//
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Context.X64StackFrame->Rip += Context.X64StackFrame->VmcsExitInstructionLength;
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return 0;
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}
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