427e357342
Add module that initializes a CPU for the SMM environment and installs the first level SMI handler. This module along with the SMM IPL and SMM Core provide the services required for DXE_SMM_DRIVERS to register hardware and software SMI handlers. CPU specific features are abstracted through the SmmCpuFeaturesLib Platform specific features are abstracted through the SmmCpuPlatformHookLib Several PCDs are added to enable/disable features and configure settings for the PiSmmCpuDxeSmm module [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18647 6f19259b-4bc3-4df7-8a09-765794883524
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
/** @file
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X64 processor specific header file to enable SMM profile.
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Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _SMM_PROFILE_ARCH_H_
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#define _SMM_PROFILE_ARCH_H_
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#pragma pack (1)
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typedef struct _MSR_DS_AREA_STRUCT {
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UINT64 BTSBufferBase;
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UINT64 BTSIndex;
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UINT64 BTSAbsoluteMaximum;
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UINT64 BTSInterruptThreshold;
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UINT64 PEBSBufferBase;
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UINT64 PEBSIndex;
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UINT64 PEBSAbsoluteMaximum;
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UINT64 PEBSInterruptThreshold;
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UINT64 PEBSCounterReset[2];
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UINT64 Reserved;
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} MSR_DS_AREA_STRUCT;
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typedef struct _BRANCH_TRACE_RECORD {
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UINT64 LastBranchFrom;
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UINT64 LastBranchTo;
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UINT64 Rsvd0 : 4;
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UINT64 BranchPredicted : 1;
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UINT64 Rsvd1 : 59;
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} BRANCH_TRACE_RECORD;
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typedef struct _PEBS_RECORD {
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UINT64 Rflags;
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UINT64 LinearIP;
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UINT64 Rax;
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UINT64 Rbx;
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UINT64 Rcx;
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UINT64 Rdx;
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UINT64 Rsi;
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UINT64 Rdi;
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UINT64 Rbp;
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UINT64 Rsp;
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UINT64 R8;
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UINT64 R9;
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UINT64 R10;
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UINT64 R11;
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UINT64 R12;
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UINT64 R13;
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UINT64 R14;
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UINT64 R15;
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} PEBS_RECORD;
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#pragma pack ()
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#define PHYSICAL_ADDRESS_MASK ((1ull << 52) - SIZE_4KB)
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/**
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Update page table to map the memory correctly in order to make the instruction
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which caused page fault execute successfully. And it also save the original page
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table to be restored in single-step exception.
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@param PageTable PageTable Address.
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@param PFAddress The memory address which caused page fault exception.
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@param CpuIndex The index of the processor.
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@param ErrorCode The Error code of exception.
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@param IsValidPFAddress The flag indicates if SMM profile data need be added.
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**/
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VOID
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RestorePageTableAbove4G (
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UINT64 *PageTable,
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UINT64 PFAddress,
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UINTN CpuIndex,
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UINTN ErrorCode,
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BOOLEAN *IsValidPFAddress
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);
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/**
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Create SMM page table for S3 path.
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**/
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VOID
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InitSmmS3Cr3 (
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VOID
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);
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/**
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Allocate pages for creating 4KB-page based on 2MB-page when page fault happens.
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**/
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VOID
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InitPagesForPFHandler (
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VOID
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);
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#endif // _SMM_PROFILE_ARCH_H_
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