3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
55 lines
2.1 KiB
C
55 lines
2.1 KiB
C
/**
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Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@file
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PchRegsRcrb.h
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@brief
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Register names for VLV Chipset Configuration Registers
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values of bits within the registers
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
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- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without <generation_name> inserted.
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**/
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#ifndef _PCH_REGS_RCRB_H_
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#define _PCH_REGS_RCRB_H_
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///
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/// Chipset Configuration Registers (Memory space)
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/// RCBA
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///
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#define R_PCH_RCRB_GCS 0x00 // General Control and Status
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#define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size
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#define B_PCH_RCRB_GCS_BBS (BIT11 | BIT10) // Boot BIOS Straps
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#define V_PCH_RCRB_GCS_BBS_SPI (3 << 10) // Boot BIOS strapped to SPI
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#define V_PCH_RCRB_GCS_BBS_LPC (0 << 10) // Boot BIOS strapped to LPC
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#define B_PCH_RCRB_GCS_TS BIT1 // Top Swap
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#define B_PCH_RCRB_GCS_BILD BIT0 // BIOS Interface Lock-Down
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#endif
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