d6af9cabad
Update Flat32.S to match Flat32.asm. A sync was missed, so Flat32.S is calling SecStartup instead of PlatformSecLibStartup which is causing a boot failures with GCC builds because the caches are not initialized correctly when the call to PlatformSecLibStartup is not performed. Cc: Kelly Steele <kelly.steele@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Kelly Steele <kelly.steele@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19306 6f19259b-4bc3-4df7-8a09-765794883524
803 lines
23 KiB
ArmAsm
803 lines
23 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2013 - 2015 Intel Corporation.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# Flat32.S
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#
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# Abstract:
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#
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# This is the code that goes from real-mode to protected mode.
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# It consumes the reset vector, configures the stack.
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#
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#
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#------------------------------------------------------------------------------
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.macro RET32
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jmp *%esp
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.endm
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#
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# ROM/SPI/MEMORY Definitions
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#
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.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) # Memory Base Address = 0
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.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) # DDR3 Memory Size = 2GB
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.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) # eSRAM Memory Size = 512K
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.equ QUARK_STACK_SIZE_BYTES, (0x008000) # Quark stack size = 32K
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#
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# RTC/CMOS definitions
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#
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.equ RTC_INDEX, (0x70)
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.equ NMI_DISABLE, (0x80) # Bit7=1 disables NMI
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.equ NMI_ENABLE, (0x00) # Bit7=0 disables NMI
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.equ RTC_DATA, (0x71)
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#
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# PCI Configuration definitions
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#
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.equ PCI_CFG, (0x80000000) # PCI configuration access mechanism
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.equ PCI_ADDRESS_PORT, (0xCF8)
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.equ PCI_DATA_PORT, (0xCFC)
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#
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# Quark PCI devices
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#
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.equ HOST_BRIDGE_PFA, (0x0000) # B0:D0:F0 (Host Bridge)
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.equ ILB_PFA, (0x00F8) # B0:D31:F0 (Legacy Block)
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#
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# ILB PCI Config Registers
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#
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.equ BDE, (0x0D4) # BIOS Decode Enable register
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.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) # Decode all BIOS decode ranges
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#
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# iLB Reset Register
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#
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.equ ILB_RESET_REG, (0x0CF9)
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.equ CF9_WARM_RESET, (0x02)
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.equ CF9_COLD_RESET, (0x08)
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#
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# Host Bridge PCI Config Registers
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#
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.equ MESSAGE_BUS_CONTROL_REG, (0xD0) # Message Bus Control Register
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.equ SB_OPCODE_FIELD, (0x18) # Bit location of Opcode field
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.equ OPCODE_SIDEBAND_REG_READ, (0x10) # Read opcode
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.equ OPCODE_SIDEBAND_REG_WRITE, (0x11) # Write opcode
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.equ OPCODE_SIDEBAND_ALT_REG_READ, (0x06) # Alternate Read opcode
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.equ OPCODE_SIDEBAND_ALT_REG_WRITE, (0x07) # Alternate Write opcode
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.equ OPCODE_WARM_RESET_REQUEST, (0xF4) # Reset Warm
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.equ OPCODE_COLD_RESET_REQUEST, (0xF5) # Reset Cold
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.equ SB_PORT_FIELD, (0x10) # Bit location of Port ID field
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.equ MEMORY_ARBITER_PORT_ID, (0x00)
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.equ HOST_BRIDGE_PORT_ID, (0x03)
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.equ RMU_PORT_ID, (0x04)
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.equ MEMORY_MANAGER_PORT_ID, (0x05)
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.equ SOC_UNIT_PORT_ID, (0x31)
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.equ SB_ADDR_FIELD, (0x08) # Bit location of Register field
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.equ SB_BE_FIELD, (0x04) # Bit location of Byte Enables field
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.equ ALL_BYTE_EN, (0x0F) # All Byte Enables
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.equ MESSAGE_DATA_REG, (0xD4) # Message Data Register
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#
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# Memory Arbiter Config Registers
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#
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.equ AEC_CTRL_OFFSET, (0x00)
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#
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# Host Bridge Config Registers
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#
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.equ HMISC2_OFFSET, (0x03) # PCI configuration access mechanism
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.equ OR_PM_FIELD, (0x10)
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.equ SMI_EN, (0x00080000)
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.equ HMBOUND_OFFSET, (0x08)
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.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
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.equ HMBOUND_LOCK, (0x01)
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.equ HECREG_OFFSET, (0x09)
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.equ EC_BASE, (0xE0000000)
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.equ EC_ENABLE, (0x01)
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.equ HLEGACY_OFFSET, (0x0A)
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.equ NMI, (0x00004000)
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.equ SMI, (0x00001000)
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.equ INTR, (0x00000400)
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#
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# Memory Manager Config Registers
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#
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.equ ESRAMPGCTRL_BLOCK_OFFSET, (0x82)
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.equ BLOCK_ENABLE_PG, (0x10000000)
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.equ BIMRVCTL_OFFSET, (0x19)
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.equ ENABLE_IMR_INTERRUPT, (0x80000000)
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#
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# SOC UNIT Debug Registers
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#
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.equ CFGSTICKY_W1_OFFSET, (0x50)
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.equ FORCE_COLD_RESET, (0x00000001)
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.equ CFGSTICKY_RW_OFFSET, (0x51)
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.equ RESET_FOR_ESRAM_LOCK, (0x00000020)
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.equ RESET_FOR_HMBOUND_LOCK, (0x00000040)
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.equ CFGNONSTICKY_W1_OFFSET, (0x52)
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.equ FORCE_WARM_RESET, (0x00000001)
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#
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# CR0 cache control bit definition
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#
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.equ CR0_CACHE_DISABLE, 0x040000000
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.equ CR0_NO_WRITE, 0x020000000
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ASM_GLOBAL ASM_PFX(PcdGet32(PcdEsramStage1Base))
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#
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# Contrary to the name, this file contains 16 bit code as well.
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#
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.text
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#----------------------------------------------------------------------------
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#
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# Procedure: _ModuleEntryPoint
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#
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# Input: None
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#
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# Output: None
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#
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# Destroys: Assume all registers
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#
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# Description:
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#
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# Transition to non-paged flat-model protected mode from a
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# hard-coded GDT that provides exactly two descriptors.
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# This is a bare bones transition to protected mode only
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# used for a while in PEI and possibly DXE.
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#
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# After enabling protected mode, a far jump is executed to
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# transfer to PEI using the newly loaded GDT.
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#
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# Return: None
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#
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#----------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
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ASM_PFX(_ModuleEntryPoint):
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#
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# Warm Reset (INIT#) check.
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#
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.byte 0xbe,0x00,0xf0 #movw $0xF000, %si
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.byte 0x8e,0xde #movw %si, %ds
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.byte 0xbe,0xf0,0xff #movw $0xFFF0, %si
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.byte 0x80,0x3c,0xea #cmpb $0xEA, (%si) # Is it warm reset ?
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jne NotWarmReset # Jump if not.
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.byte 0xb0,0x08 #movb $0x08, %al
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.byte 0xba,0xf9,0x0c #movw $0xcf9, %dx
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.byte 0xee #outb %al, %dx
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.byte 0xb0,0x55 #movb $0x55, %al
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.byte 0xe6,0x80 #outb %al, $0x80
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jmp .
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NotWarmReset:
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.byte 0x66,0x8b,0xe8 #movl %eax, %ebp
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#
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# Load the GDT table in GdtDesc
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#
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.byte 0x66,0xbe #movl $GdtDesc, %esi
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.long GdtDesc
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.byte 0x66,0x2e,0x0f,0x01,0x14 #lgdt %cs:(%si)
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#
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# Transition to 16 bit protected mode
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#
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.byte 0x0f,0x20,0xc0 #movl %cr0, %eax # Get control register 0
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.byte 0x66,0x83,0xc8,0x03 #orl $0x0000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)
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.byte 0x0f,0x22,0xc0 #movl %eax, %cr0 # Activate protected mode
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#
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# Now we're in 16 bit protected mode
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# Set up the selectors for 32 bit protected mode entry
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#
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.byte 0xb8 #movw SYS_DATA_SEL, %ax
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.word SYS_DATA_SEL
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.byte 0x8e,0xd8 #movw %ax, %ds
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.byte 0x8e,0xc0 #movw %ax, %es
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.byte 0x8e,0xe0 #movw %ax, %fs
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.byte 0x8e,0xe8 #movw %ax, %gs
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.byte 0x8e,0xd0 #movw %ax, %ss
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#
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# Transition to Flat 32 bit protected mode
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# The jump to a far pointer causes the transition to 32 bit mode
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#
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.byte 0x66,0xbe #movl ProtectedModeEntryLinearAddress, %esi
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.long ProtectedModeEntryLinearAddress
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.byte 0x66,0x2e,0xff,0x2c #jmp %cs:(%esi)
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#
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# Protected mode portion initializes stack, configures cache, and calls C entry point
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#
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#----------------------------------------------------------------------------
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#
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# Procedure: ProtectedModeEntryPoint
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#
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# Input: Executing in 32 Bit Protected (flat) mode
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# cs: 0-4GB
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# ds: 0-4GB
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# es: 0-4GB
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# fs: 0-4GB
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# gs: 0-4GB
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# ss: 0-4GB
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#
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# Output: This function never returns
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#
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# Destroys:
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# ecx
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# edi
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# esi
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# esp
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#
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# Description:
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# Perform any essential early platform initilaisation
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# Setup a stack
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# Transfer control to EDKII code in eSRAM
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#
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#----------------------------------------------------------------------------
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ProtectedModeEntryPoint:
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leal L0, %esp
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jmp stackless_EarlyPlatformInit
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L0:
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#
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# Set up stack pointer
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#
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movl ASM_PFX(PcdGet32(PcdEsramStage1Base)), %esp
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movl $QUARK_STACK_SIZE_BYTES, %esi
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addl %esi, %esp # ESP = top of stack (stack grows downwards).
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#
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# Store the the BIST value in EBP
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#
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movl $0, %ebp # No processor BIST on Quark
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#
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# Push processor count to stack first, then BIST status (AP then BSP)
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#
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movl $1, %eax
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cpuid
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shrl $16, %ebx
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andl $0x000000FF, %ebx
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cmpb $1, %bl
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jae PushProcessorCount
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#
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# Some processors report 0 logical processors. Effectively 0 = 1.
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# So we fix up the processor count
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#
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incl %ebx
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PushProcessorCount:
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pushl %ebx
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#
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# We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
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# for all processor threads
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#
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xorl %ecx, %ecx
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movb %bl, %cl
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PushBist:
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pushl %ebp
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loop PushBist
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#
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# Pass Control into the PEI Core
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#
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call PlatformSecLibStartup
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#
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# PEI Core should never return to here, this is just to capture an invalid return.
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#
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jmp .
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#----------------------------------------------------------------------------
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#
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# Procedure: stackless_EarlyPlatformInit
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#
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# Input: esp - Return address
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#
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# Output: None
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#
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# Destroys: Assume all registers
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#
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# Description:
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# Any early platform initialisation required
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#
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# Return:
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# None
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#
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#----------------------------------------------------------------------------
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stackless_EarlyPlatformInit:
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#
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# Save return address
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#
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movl %esp, %ebp
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#
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# Ensure cache is disabled.
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#
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movl %cr0, %eax
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orl $(CR0_CACHE_DISABLE + CR0_NO_WRITE), %eax
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invd
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movl %eax, %cr0
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#
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# Disable NMI operation
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# Good convention suggests you should read back RTC data port after
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# accessing the RTC index port.
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#
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movb $(NMI_DISABLE), %al
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movw $(RTC_INDEX), %dx
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outb %al, %dx
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movw $(RTC_DATA), %dx
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inb %dx, %al
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#
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# Disable SMI (Disables SMI wire, not SMI messages)
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#
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movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMISC2_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L1, %esp
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jmp stackless_SideBand_Read
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L1:
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andl $(~SMI_EN), %eax
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movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMISC2_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L2, %esp
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jmp stackless_SideBand_Write
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L2:
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#
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# Before we get going, check SOC Unit Registers to see if we are required to issue a warm/cold reset
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#
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movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGNONSTICKY_W1_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L3, %esp
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jmp stackless_SideBand_Read
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L3:
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andl $(FORCE_WARM_RESET), %eax
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jz TestForceColdReset # Zero means bit clear, we're not requested to warm reset so continue as normal
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jmp IssueWarmReset
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TestForceColdReset:
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movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGNONSTICKY_W1_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L4, %esp
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jmp stackless_SideBand_Read
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L4:
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andl $(FORCE_COLD_RESET), %eax
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jz TestHmboundLock # Zero means bit clear, we're not requested to cold reset so continue as normal
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jmp IssueColdReset
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#
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# Before setting HMBOUND, check it's not locked
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#
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TestHmboundLock:
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movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMBOUND_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L5, %esp
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jmp stackless_SideBand_Read
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L5:
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andl $(HMBOUND_LOCK), %eax
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jz ConfigHmbound # Zero means bit clear, we have the config we want so continue as normal
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#
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# Failed to config - store sticky bit debug
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#
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movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L6, %esp
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jmp stackless_SideBand_Read
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L6:
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orl $(RESET_FOR_HMBOUND_LOCK), %eax
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movl $((OPCODE_SIDEBAND_ALT_REG_WRITE << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L7, %esp
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jmp stackless_SideBand_Write
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L7:
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jmp IssueWarmReset
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#
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# Set up the HMBOUND register
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#
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ConfigHmbound:
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movl $(HMBOUND_ADDRESS), %eax # Data (Set HMBOUND location)
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movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMBOUND_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L8, %esp
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jmp stackless_SideBand_Write
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L8:
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#
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# Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND violation occurs.
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#
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movl $(ENABLE_IMR_INTERRUPT), %eax # Data (Set interrupt enable mask)
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movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (BIMRVCTL_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L9, %esp
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jmp stackless_SideBand_Write
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L9:
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#
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# Set eSRAM address
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#
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movl ASM_PFX(PcdGet32(PcdEsramStage1Base)), %eax # Data (Set eSRAM location)
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shr $(0x18), %eax
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addl $(BLOCK_ENABLE_PG), %eax
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movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (ESRAMPGCTRL_BLOCK_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L10, %esp
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jmp stackless_SideBand_Write
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L10:
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#
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# Check that we're not blocked from setting the config that we want.
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#
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movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (ESRAMPGCTRL_BLOCK_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L11, %esp
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jmp stackless_SideBand_Read
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L11:
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andl $(BLOCK_ENABLE_PG), %eax
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jnz ConfigPci # Non-zero means bit set, we have the config we want so continue as normal
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#
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# Failed to config - store sticky bit debug
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#
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movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx
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leal L12, %esp
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jmp stackless_SideBand_Read
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L12:
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orl $(RESET_FOR_ESRAM_LOCK), %eax # Set the bit we're interested in
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movl $((OPCODE_SIDEBAND_ALT_REG_WRITE << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx
|
|
leal L13, %esp
|
|
jmp stackless_SideBand_Write
|
|
L13:
|
|
jmp IssueWarmReset
|
|
|
|
#
|
|
# Enable PCIEXBAR
|
|
#
|
|
ConfigPci:
|
|
movl $(EC_BASE + EC_ENABLE), %eax # Data
|
|
movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_ARBITER_PORT_ID << SB_PORT_FIELD) | (AEC_CTRL_OFFSET << SB_ADDR_FIELD)), %ecx
|
|
leal L14, %esp
|
|
jmp stackless_SideBand_Write
|
|
L14:
|
|
|
|
movl $(EC_BASE + EC_ENABLE), %eax # Data
|
|
movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HECREG_OFFSET << SB_ADDR_FIELD)), %ecx
|
|
leal L15, %esp
|
|
jmp stackless_SideBand_Write
|
|
L15:
|
|
|
|
#
|
|
# Open up full 8MB SPI decode
|
|
#
|
|
movl $(PCI_CFG | (ILB_PFA << 8) | BDE), %ebx # PCI Configuration address
|
|
movl $(DECODE_ALL_REGIONS_ENABLE), %eax
|
|
leal L16, %esp
|
|
jmp stackless_PCIConfig_Write
|
|
L16:
|
|
|
|
#
|
|
# Enable NMI operation
|
|
# Good convention suggests you should read back RTC data port after
|
|
# accessing the RTC index port.
|
|
#
|
|
movb $(NMI_ENABLE), %al
|
|
movw $(RTC_INDEX), %dx
|
|
outb %al, %dx
|
|
movw $(RTC_DATA), %dx
|
|
inb %dx, %al
|
|
|
|
#
|
|
# Clear Host Bridge SMI, NMI, INTR fields
|
|
#
|
|
movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HLEGACY_OFFSET << SB_ADDR_FIELD)), %ecx
|
|
leal L21, %esp
|
|
jmp stackless_SideBand_Read
|
|
L21:
|
|
andl $~(NMI + SMI + INTR), %eax # Clear NMI, SMI, INTR fields
|
|
movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HLEGACY_OFFSET << SB_ADDR_FIELD)), %ecx
|
|
leal L22, %esp
|
|
jmp stackless_SideBand_Write
|
|
L22:
|
|
|
|
#
|
|
# Restore return address
|
|
#
|
|
movl %ebp, %esp
|
|
RET32
|
|
|
|
IssueWarmReset:
|
|
#
|
|
# Issue Warm Reset request to Remote Management Unit via iLB
|
|
#
|
|
movw $(CF9_WARM_RESET), %ax
|
|
movw $(ILB_RESET_REG), %dx
|
|
outw %ax, %dx
|
|
jmp . # Stay here until we are reset.
|
|
|
|
IssueColdReset:
|
|
#
|
|
# Issue Cold Reset request to Remote Management Unit via iLB
|
|
#
|
|
movw $(CF9_COLD_RESET), %ax
|
|
movw $(ILB_RESET_REG), %dx
|
|
outw %ax, %dx
|
|
jmp . # Stay here until we are reset.
|
|
|
|
#----------------------------------------------------------------------------
|
|
#
|
|
# Procedure: stackless_SideBand_Read
|
|
#
|
|
# Input: esp - return address
|
|
# ecx[15:8] - Register offset
|
|
# ecx[23:16] - Port ID
|
|
# ecx[31:24] - Opcode
|
|
#
|
|
# Output: eax - Data read
|
|
#
|
|
# Destroys:
|
|
# eax
|
|
# ebx
|
|
# cl
|
|
# esi
|
|
#
|
|
# Description:
|
|
# Perform requested sideband read
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
stackless_SideBand_Read:
|
|
|
|
movl %esp, %esi # Save the return address
|
|
|
|
#
|
|
# Load the SideBand Packet Register to generate the transaction
|
|
#
|
|
movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_BUS_CONTROL_REG)), %ebx # PCI Configuration address
|
|
movb $(ALL_BYTE_EN << SB_BE_FIELD), %cl # Set all Byte Enable bits
|
|
xchgl %ecx, %eax
|
|
leal L17, %esp
|
|
jmp stackless_PCIConfig_Write
|
|
L17:
|
|
xchgl %ecx, %eax
|
|
|
|
#
|
|
# Read the SideBand Data Register
|
|
#
|
|
movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_DATA_REG)), %ebx # PCI Configuration address
|
|
leal L18, %esp
|
|
jmp stackless_PCIConfig_Read
|
|
L18:
|
|
|
|
movl %esi, %esp # Restore the return address
|
|
RET32
|
|
|
|
|
|
#----------------------------------------------------------------------------
|
|
#
|
|
# Procedure: stackless_SideBand_Write
|
|
#
|
|
# Input: esp - return address
|
|
# eax - Data
|
|
# ecx[15:8] - Register offset
|
|
# ecx[23:16] - Port ID
|
|
# ecx[31:24] - Opcode
|
|
#
|
|
# Output: None
|
|
#
|
|
# Destroys:
|
|
# ebx
|
|
# cl
|
|
# esi
|
|
#
|
|
# Description:
|
|
# Perform requested sideband write
|
|
#
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
stackless_SideBand_Write:
|
|
|
|
movl %esp, %esi # Save the return address
|
|
|
|
#
|
|
# Load the SideBand Data Register with the data
|
|
#
|
|
movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_DATA_REG)), %ebx # PCI Configuration address
|
|
leal L19, %esp
|
|
jmp stackless_PCIConfig_Write
|
|
L19:
|
|
|
|
#
|
|
# Load the SideBand Packet Register to generate the transaction
|
|
#
|
|
movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_BUS_CONTROL_REG)), %ebx # PCI Configuration address
|
|
movb $(ALL_BYTE_EN << SB_BE_FIELD), %cl # Set all Byte Enable bits
|
|
xchgl %ecx, %eax
|
|
leal L20, %esp
|
|
jmp stackless_PCIConfig_Write
|
|
L20:
|
|
xchgl %ecx, %eax
|
|
|
|
movl %esi, %esp # Restore the return address
|
|
RET32
|
|
|
|
|
|
#----------------------------------------------------------------------------
|
|
#
|
|
# Procedure: stackless_PCIConfig_Write
|
|
#
|
|
# Input: esp - return address
|
|
# eax - Data to write
|
|
# ebx - PCI Config Address
|
|
#
|
|
# Output: None
|
|
#
|
|
# Destroys:
|
|
# dx
|
|
#
|
|
# Description:
|
|
# Perform a DWORD PCI Configuration write
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
stackless_PCIConfig_Write:
|
|
|
|
#
|
|
# Write the PCI Config Address to the address port
|
|
#
|
|
xchgl %ebx, %eax
|
|
movw $(PCI_ADDRESS_PORT), %dx
|
|
outl %eax, %dx
|
|
xchgl %ebx, %eax
|
|
|
|
#
|
|
# Write the PCI DWORD Data to the data port
|
|
#
|
|
movw $(PCI_DATA_PORT), %dx
|
|
outl %eax, %dx
|
|
|
|
RET32
|
|
|
|
|
|
#----------------------------------------------------------------------------
|
|
#
|
|
# Procedure: stackless_PCIConfig_Read
|
|
#
|
|
# Input: esp - return address
|
|
# ebx - PCI Config Address
|
|
#
|
|
# Output: eax - Data read
|
|
#
|
|
# Destroys:
|
|
# eax
|
|
# dx
|
|
#
|
|
# Description:
|
|
# Perform a DWORD PCI Configuration read
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
stackless_PCIConfig_Read:
|
|
|
|
#
|
|
# Write the PCI Config Address to the address port
|
|
#
|
|
xchgl %ebx, %eax
|
|
movw $(PCI_ADDRESS_PORT), %dx
|
|
outl %eax, %dx
|
|
xchgl %ebx, %eax
|
|
|
|
#
|
|
# Read the PCI DWORD Data from the data port
|
|
#
|
|
movw $(PCI_DATA_PORT), %dx
|
|
inl %dx, %eax
|
|
|
|
RET32
|
|
|
|
|
|
#
|
|
# ROM-based Global-Descriptor Table for the Tiano PEI Phase
|
|
#
|
|
.align 16
|
|
#
|
|
# GDT[0]: 000h: Null entry, never used.
|
|
#
|
|
|
|
GDT_BASE:
|
|
BootGdtTable:
|
|
# null descriptor
|
|
.equ NULL_SEL, . - GDT_BASE # Selector [0]
|
|
.word 0 # limit 15:0
|
|
.word 0 # base 15:0
|
|
.byte 0 # base 23:16
|
|
.byte 0 # type
|
|
.byte 0 # limit 19:16, flags
|
|
.byte 0 # base 31:24
|
|
|
|
# linear data segment descriptor
|
|
.equ LINEAR_SEL, . - GDT_BASE # Selector [0x8]
|
|
.word 0xFFFF # limit 0xFFFFF
|
|
.word 0 # base 0
|
|
.byte 0
|
|
.byte 0x92 # present, ring 0, data, expand-up, writable
|
|
.byte 0xCF # page-granular, 32-bit
|
|
.byte 0
|
|
|
|
# linear code segment descriptor
|
|
.equ LINEAR_CODE_SEL, . - GDT_BASE # Selector [0x10]
|
|
.word 0xFFFF # limit 0xFFFFF
|
|
.word 0 # base 0
|
|
.byte 0
|
|
.byte 0x9A # present, ring 0, data, expand-up, writable
|
|
.byte 0xCF # page-granular, 32-bit
|
|
.byte 0
|
|
|
|
# system data segment descriptor
|
|
.equ SYS_DATA_SEL, . - GDT_BASE # Selector [0x18]
|
|
.word 0xFFFF # limit 0xFFFFF
|
|
.word 0 # base 0
|
|
.byte 0
|
|
.byte 0x92 # present, ring 0, data, expand-up, writable
|
|
.byte 0xCF # page-granular, 32-bit
|
|
.byte 0
|
|
|
|
# system code segment descriptor
|
|
.equ SYS_CODE_SEL, . - GDT_BASE
|
|
.word 0xFFFF # limit 0xFFFFF
|
|
.word 0 # base 0
|
|
.byte 0
|
|
.byte 0x9A # present, ring 0, data, expand-up, writable
|
|
.byte 0xCF # page-granular, 32-bit
|
|
.byte 0
|
|
|
|
# spare segment descriptor
|
|
.equ SYS16_CODE_SEL, . - GDT_BASE
|
|
.word 0xffff # limit 0xFFFFF
|
|
.word 0 # base 0
|
|
.byte 0x0f
|
|
.byte 0x9b # present, ring 0, data, expand-up, writable
|
|
.byte 0 # page-granular, 32-bit
|
|
.byte 0
|
|
|
|
# spare segment descriptor
|
|
.equ SYS16_DATA_SEL, . - GDT_BASE
|
|
.word 0xffff # limit 0xFFFFF
|
|
.word 0 # base 0
|
|
.byte 0
|
|
.byte 0x93 # present, ring 0, data, expand-up, not-writable
|
|
.byte 0 # page-granular, 32-bit
|
|
.byte 0
|
|
|
|
# spare segment descriptor
|
|
.equ SPARE5_SEL, . - GDT_BASE
|
|
.word 0 # limit 0xFFFFF
|
|
.word 0 # base 0
|
|
.byte 0
|
|
.byte 0 # present, ring 0, data, expand-up, writable
|
|
.byte 0 # page-granular, 32-bit
|
|
.byte 0
|
|
.equ GDT_SIZE, . - GDT_BASE
|
|
|
|
#
|
|
# GDT Descriptor
|
|
#
|
|
GdtDesc: # GDT descriptor
|
|
.word GDT_SIZE - 1
|
|
.long BootGdtTable
|
|
|
|
ProtectedModeEntryLinearAddress:
|
|
ProtectedModeEntryLinearOffset:
|
|
.long ProtectedModeEntryPoint
|
|
.word LINEAR_CODE_SEL
|