d05ca26cb8
ArmPlatformGetPrimaryCoreMpId returns the MPID of the primary core. The primary core might not be known at build time (eg: the platform allows the boot CPU to be changed through board config). This function is used during the secondary core stack initialization to know the position of the secondary core in the SoC. A secondary core that is at the position N, with N greater than the primary core position, will be at the position N-1 in the list of secondary stacks (the primary core has its own separate bigger stack). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14345 6f19259b-4bc3-4df7-8a09-765794883524
107 lines
2.9 KiB
NASM
107 lines
2.9 KiB
NASM
//
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Base.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmCortexA9.h>
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#include <AutoGen.h>
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmGetCpuCountPerCluster
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EXPORT ArmPlatformIsPrimaryCore
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EXPORT ArmPlatformGetPrimaryCoreMpId
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IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore
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IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask
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AREA RTSMHelper, CODE, READONLY
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// IN None
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// OUT r0 = SCU Base Address
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ArmGetScuBaseAddress FUNCTION
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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ENDFUNC
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//UINTN
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//ArmPlatformGetPrimaryCoreMpId (
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// VOID
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// );
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ArmPlatformGetPrimaryCoreMpId FUNCTION
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LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)
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ldr r0, [r0]
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bx lr
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ENDFUNC
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// IN None
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// OUT r0 = number of cores present in the system
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ArmGetCpuCountPerCluster FUNCTION
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stmfd SP!, {r1-r2}
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// Read CP15 MIDR
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mrc p15, 0, r1, c0, c0, 0
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// Check if the CPU is A15
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mov r1, r1, LSR #4
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mov r0, #ARM_CPU_TYPE_MASK
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and r1, r1, r0
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mov r0, #ARM_CPU_TYPE_A15
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cmp r1, r0
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beq _Read_cp15_reg
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_CPU_is_not_A15
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mov r2, lr ; Save link register
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bl ArmGetScuBaseAddress ; Read SCU Base Address
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mov lr, r2 ; Restore link register val
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ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count
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b _Return
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_Read_cp15_reg
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mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count
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lsr r0, #24
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_Return
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and r0, r0, #3
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// Add '1' to the number of CPU on the Cluster
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add r0, r0, #1
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ldmfd SP!, {r1-r2}
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bx lr
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ENDFUNC
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//UINTN
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//ArmPlatformIsPrimaryCore (
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// IN UINTN MpId
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// );
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ArmPlatformIsPrimaryCore FUNCTION
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LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
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ldr r1, [r1]
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and r0, r0, r1
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LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
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ldr r1, [r1]
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cmp r0, r1
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moveq r0, #1
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movne r0, #0
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bx lr
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ENDFUNC
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END
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