d064a6f790
In ResetVector, if create page table, its highest address is fixed because after page table, code layout is fixed(4K for normal code, and another 4K only contains reset vector code). Today's implementation organizes the page table as following if 1G page table is used: 4G-16K: PML4 page (PML4[0] points to 4G-12K) 4G-12K: PDP page CR3 is set to 4G-16K When 2M page table is used, the layout is as following: 4G-32K: PML4 page (PML4[0] points to 4G-28K) 4G-28K: PDP page (PDP entries point to PD pages) 4G-24K: PD page mapping 0-1G 4G-20K: PD page mapping 1-2G 4G-16K: PD page mapping 2-3G 4G-12K: PD page mapping 3-4G CR3 is set to 4G-32K CR3 doesn't point to a fixed location which is a bit hard to debug at runtime. The new page table layout will always put PML4 in highest address When 1G page table is used, the layout is as following: 4G-16K: PDP page 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used, the layout is as following: 4G-32K: PD page mapping 0-1G 4G-28K: PD page mapping 1-2G 4G-24K: PD page mapping 2-3G 4G-20K: PD page mapping 3-4G 4G-16K: PDP page (PDP entries point to PD pages) 4G-12K: PML4 page (PML4[0] points to 4G-16K) CR3 is always set to 4G-12K So, this patch can improve debuggability by make sure the init CR3 pointing to a fixed address(4G-12K). Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
85 lines
2.0 KiB
NASM
85 lines
2.0 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Emits Page Tables for 1:1 mapping.
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; If using 1G page table, map addresses 0 - 0x8000000000 (512GB),
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; else, map addresses 0 - 0x100000000 (4GB)
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;
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; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 64
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%define ALIGN_TOP_TO_4K_FOR_PAGING
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;
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; Page table non-leaf entry attribute
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;
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%define PAGE_NLE_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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;
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; Page table big leaf entry attribute:
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; PDPTE 1GB entry or PDE 2MB entry
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;
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%define PAGE_BLE_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_DIRTY + \
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PAGE_PRESENT + \
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PAGE_SIZE)
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;
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; Page table non-leaf entry
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;
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%define PAGE_NLE(address) (ADDR_OF(address) + \
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PAGE_NLE_ATTR)
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%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)
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%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
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ALIGN 16
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%ifdef PAGE_TABLE_1G
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Pdp:
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;
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; Page-directory pointer table (512 * 1GB entries => 512GB)
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;
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%assign i 0
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%rep 512
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DQ PAGE_PDPTE_1GB(i)
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%assign i i+1
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%endrep
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%else
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Pd:
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;
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; Page-Directory (2048 * 2MB entries => 4GB)
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; Four pages below, each is pointed by one entry in Pdp.
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;
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%assign i 0
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%rep 0x800
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DQ PAGE_PDE_2MB(i)
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%assign i i+1
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%endrep
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Pdp:
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;
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; Page-directory pointer table (4 * 1GB entries => 4GB)
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;
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DQ PAGE_NLE(Pd)
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DQ PAGE_NLE(Pd + 0x1000)
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DQ PAGE_NLE(Pd + 0x2000)
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DQ PAGE_NLE(Pd + 0x3000)
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TIMES 0x1000 - ($ - Pdp) DB 0
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%endif
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Pml4:
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;
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; PML4 (1 * 512GB entry)
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;
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DQ PAGE_NLE(Pdp)
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TIMES 0x1000 - ($ - Pml4) DB 0
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EndOfPageTables:
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