18b144ea42
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10867 6f19259b-4bc3-4df7-8a09-765794883524
243 lines
7.8 KiB
C
243 lines
7.8 KiB
C
/** @file
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Public include file for Debug Port Library.
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Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "DebugAgent.h"
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/**
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Read the offset of FP / MMX / XMM registers by register index.
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@param[in] Index Register index.
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@param[out] Width Register width returned.
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@return Offset in register address range.
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**/
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UINT16
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ArchReadFxStatOffset (
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IN UINT8 Index,
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OUT UINT8 *Width
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)
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{
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if (Index < SOFT_DEBUGGER_REGISTER_ST0) {
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switch (Index) {
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case SOFT_DEBUGGER_REGISTER_FP_FCW:
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*Width = (UINT8) sizeof (UINT16);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Fcw);
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case SOFT_DEBUGGER_REGISTER_FP_FSW:
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*Width = (UINT8) sizeof (UINT16);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Fsw);
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case SOFT_DEBUGGER_REGISTER_FP_FTW:
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*Width = (UINT8) sizeof (UINT16);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Ftw);
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case SOFT_DEBUGGER_REGISTER_FP_OPCODE:
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*Width = (UINT8) sizeof (UINT16);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Opcode);
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case SOFT_DEBUGGER_REGISTER_FP_EIP:
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*Width = (UINT8) sizeof (UINTN);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Eip);
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case SOFT_DEBUGGER_REGISTER_FP_CS:
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*Width = (UINT8) sizeof (UINT16);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Cs);
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case SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET:
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*Width = (UINT8) sizeof (UINTN);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, DataOffset);
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case SOFT_DEBUGGER_REGISTER_FP_DS:
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*Width = (UINT8) sizeof (UINT16);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Ds);
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case SOFT_DEBUGGER_REGISTER_FP_MXCSR:
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*Width = (UINT8) sizeof (UINTN);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Mxcsr);
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case SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK:
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*Width = (UINT8) sizeof (UINTN);
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return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Mxcsr_Mask);
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}
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}
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if (Index < SOFT_DEBUGGER_REGISTER_XMM0) {
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*Width = 10;
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} else if (Index < SOFT_DEBUGGER_REGISTER_MM0 ) {
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*Width = 16;
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} else {
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*Width = 8;
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Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
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}
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return (UINT16)(OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, St0Mm0) + (Index - SOFT_DEBUGGER_REGISTER_ST0) * 16);
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}
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/**
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Write specified register into save CPU context.
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@param[in] CpuContext Pointer to saved CPU context.
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@param[in] Index Register index value.
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@param[in] Offset Offset in register address range.
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@param[in] Width Data width to read.
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@param[in] RegisterBuffer Pointer to input buffer with data.
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**/
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VOID
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ArchWriteRegisterBuffer (
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IN DEBUG_CPU_CONTEXT *CpuContext,
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IN UINT8 Index,
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IN UINT8 Offset,
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IN UINT8 Width,
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IN UINT8 *RegisterBuffer
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)
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{
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UINT8 *Buffer;
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if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
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Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_IA32_FX_SAVE_STATE) + Index * 4;
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} else {
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//
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// If it is MMX register, adjust its index position
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//
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if (Index >= SOFT_DEBUGGER_REGISTER_MM0) {
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Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
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}
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//
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// FPU/MMX/XMM registers
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//
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Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, &Width);
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}
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CopyMem (Buffer + Offset, RegisterBuffer, Width);
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}
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/**
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Read register value from saved CPU context.
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@param[in] CpuContext Pointer to saved CPU context.
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@param[in] Index Register index value.
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@param[in] Offset Offset in register address range
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@param[in] Width Data width to read.
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@return The address of register value.
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**/
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UINT8 *
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ArchReadRegisterBuffer (
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IN DEBUG_CPU_CONTEXT *CpuContext,
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IN UINT8 Index,
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IN UINT8 Offset,
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IN UINT8 *Width
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)
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{
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UINT8 *Buffer;
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if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
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Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_IA32_FX_SAVE_STATE) + Index * 4;
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if (*Width == 0) {
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*Width = (UINT8) sizeof (UINTN);
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}
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} else {
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//
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// FPU/MMX/XMM registers
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//
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Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, Width);
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}
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return Buffer;
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}
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/**
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Read group register of common registers.
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@param[in] CpuContext Pointer to saved CPU context.
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@param[in] RegisterGroup Pointer to Group registers.
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**/
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VOID
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ReadRegisterGroup (
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IN DEBUG_CPU_CONTEXT *CpuContext,
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IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP *RegisterGroup
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)
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{
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RegisterGroup->Cs = (UINT16) CpuContext->Cs;
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RegisterGroup->Ds = (UINT16) CpuContext->Ds;
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RegisterGroup->Es = (UINT16) CpuContext->Es;
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RegisterGroup->Fs = (UINT16) CpuContext->Fs;
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RegisterGroup->Gs = (UINT16) CpuContext->Gs;
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RegisterGroup->Ss = (UINT16) CpuContext->Ss;
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RegisterGroup->Eflags = CpuContext->Eflags;
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RegisterGroup->Ebp = CpuContext->Ebp;
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RegisterGroup->Eip = CpuContext->Eip;
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RegisterGroup->Esp = CpuContext->Esp;
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RegisterGroup->Eax = CpuContext->Eax;
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RegisterGroup->Ebx = CpuContext->Ebx;
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RegisterGroup->Ecx = CpuContext->Ecx;
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RegisterGroup->Edx = CpuContext->Edx;
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RegisterGroup->Esi = CpuContext->Esi;
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RegisterGroup->Edi = CpuContext->Edi;
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RegisterGroup->Dr0 = CpuContext->Dr0;
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RegisterGroup->Dr1 = CpuContext->Dr1;
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RegisterGroup->Dr2 = CpuContext->Dr2;
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RegisterGroup->Dr3 = CpuContext->Dr3;
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RegisterGroup->Dr6 = CpuContext->Dr6;
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RegisterGroup->Dr7 = CpuContext->Dr7;
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}
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/**
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Initialize IDT entries to support source level debug.
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**/
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VOID
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InitializeDebugIdt (
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VOID
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)
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{
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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UINTN InterruptHandler;
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IA32_DESCRIPTOR IdtDescriptor;
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UINTN Index;
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UINT16 CodeSegment;
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AsmReadIdtr (&IdtDescriptor);
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//
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// Use current CS as the segment selector of interrupt gate in IDT
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//
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CodeSegment = AsmReadCs ();
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
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for (Index = 0; Index < 20; Index ++) {
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if ((PcdGet32 (PcdExceptionsIgnoredByDebugger) & (1 << Index)) != 0) {
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//
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// If the exception is masked to be reserved, skip it
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//
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continue;
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}
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InterruptHandler = (UINTN)&Exception0Handle + Index * ExceptionStubHeaderSize;
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IdtEntry[Index].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
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IdtEntry[Index].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
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IdtEntry[Index].Bits.Selector = CodeSegment;
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IdtEntry[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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}
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InterruptHandler = (UINTN) &TimerInterruptHandle;
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
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IdtEntry[Index].Bits.Selector = CodeSegment;
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IdtEntry[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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}
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