3707dee3da
Now that we dropped all ArmPlatformGlobalVariableLib dependencies, there is no longer a need to allocate and clear out the global variable region in the PrePeiCore init code. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18994 6f19259b-4bc3-4df7-8a09-765794883524
79 lines
2.0 KiB
C
79 lines
2.0 KiB
C
/** @file
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* Main file supporting the transition to PEI Core in Normal World for Versatile Express
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __PREPEICORE_H_
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#define __PREPEICORE_H_
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#include <Library/ArmLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <PiPei.h>
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#include <Ppi/TemporaryRamSupport.h>
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VOID
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CreatePpiList (
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OUT UINTN *PpiListSize,
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OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
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);
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EFI_STATUS
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EFIAPI
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PrePeiCoreTemporaryRamSupport (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
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IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
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IN UINTN CopySize
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);
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VOID
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SecSwitchStack (
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INTN StackDelta
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);
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// Vector Table for Pei Phase
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VOID PeiVectorTable (VOID);
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VOID
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EFIAPI
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PrimaryMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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);
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/*
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* This is the main function for secondary cores. They loop around until a non Null value is written to
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* SYS_FLAGS register.The SYS_FLAGS register is platform specific.
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* Note:The secondary cores, while executing secondary_main, assumes that:
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* : SGI 0 is configured as Non-secure interrupt
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* : Priority Mask is configured to allow SGI 0
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* : Interrupt Distributor and CPU interfaces are enabled
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*
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*/
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN MpId
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);
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VOID
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PeiCommonExceptionEntry (
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IN UINT32 Entry,
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IN UINTN LR
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);
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#endif
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