d9be0f66ff
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=695 Within function CoreRestoreTpl(), left shift a negative value -2 is used in: "while (((-2 << NewTpl) & gEventPending) != 0) {" which involves undefined behavior. According to the C11 spec, Section 6.5.7: > 4 The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated > bits are filled with zeros. If E1 has an unsigned type, the value > of the result is E1 * 2^E2 , reduced modulo one more than the > maximum value representable in the result type. If E1 has a signed > type and nonnegative value, and E1 * 2^E2 is representable in the > result type, then that is the resulting value; otherwise, the > behavior is undefined. This commit refines the code logic to avoid left shifting the negative value. Cc: Steven Shi <steven.shi@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
155 lines
3.2 KiB
C
155 lines
3.2 KiB
C
/** @file
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Task priority (TPL) functions.
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Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "DxeMain.h"
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#include "Event.h"
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/**
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Set Interrupt State.
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@param Enable The state of enable or disable interrupt
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**/
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VOID
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CoreSetInterruptState (
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IN BOOLEAN Enable
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)
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{
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EFI_STATUS Status;
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BOOLEAN InSmm;
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if (gCpu == NULL) {
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return;
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}
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if (!Enable) {
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gCpu->DisableInterrupt (gCpu);
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return;
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}
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if (gSmmBase2 == NULL) {
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gCpu->EnableInterrupt (gCpu);
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return;
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}
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Status = gSmmBase2->InSmm (gSmmBase2, &InSmm);
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if (!EFI_ERROR (Status) && !InSmm) {
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gCpu->EnableInterrupt(gCpu);
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}
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}
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/**
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Raise the task priority level to the new level.
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High level is implemented by disabling processor interrupts.
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@param NewTpl New task priority level
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@return The previous task priority level
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**/
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EFI_TPL
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EFIAPI
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CoreRaiseTpl (
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IN EFI_TPL NewTpl
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)
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{
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EFI_TPL OldTpl;
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OldTpl = gEfiCurrentTpl;
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if (OldTpl > NewTpl) {
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DEBUG ((EFI_D_ERROR, "FATAL ERROR - RaiseTpl with OldTpl(0x%x) > NewTpl(0x%x)\n", OldTpl, NewTpl));
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ASSERT (FALSE);
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}
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ASSERT (VALID_TPL (NewTpl));
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//
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// If raising to high level, disable interrupts
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//
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if (NewTpl >= TPL_HIGH_LEVEL && OldTpl < TPL_HIGH_LEVEL) {
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CoreSetInterruptState (FALSE);
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}
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//
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// Set the new value
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//
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gEfiCurrentTpl = NewTpl;
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return OldTpl;
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}
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/**
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Lowers the task priority to the previous value. If the new
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priority unmasks events at a higher priority, they are dispatched.
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@param NewTpl New, lower, task priority
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**/
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VOID
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EFIAPI
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CoreRestoreTpl (
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IN EFI_TPL NewTpl
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)
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{
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EFI_TPL OldTpl;
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EFI_TPL PendingTpl;
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OldTpl = gEfiCurrentTpl;
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if (NewTpl > OldTpl) {
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DEBUG ((EFI_D_ERROR, "FATAL ERROR - RestoreTpl with NewTpl(0x%x) > OldTpl(0x%x)\n", NewTpl, OldTpl));
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ASSERT (FALSE);
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}
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ASSERT (VALID_TPL (NewTpl));
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//
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// If lowering below HIGH_LEVEL, make sure
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// interrupts are enabled
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//
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if (OldTpl >= TPL_HIGH_LEVEL && NewTpl < TPL_HIGH_LEVEL) {
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gEfiCurrentTpl = TPL_HIGH_LEVEL;
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}
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//
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// Dispatch any pending events
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//
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while (gEventPending != 0) {
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PendingTpl = (UINTN) HighBitSet64 (gEventPending);
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if (PendingTpl <= NewTpl) {
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break;
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}
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gEfiCurrentTpl = PendingTpl;
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if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {
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CoreSetInterruptState (TRUE);
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}
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CoreDispatchEventNotifies (gEfiCurrentTpl);
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}
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//
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// Set the new value
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//
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gEfiCurrentTpl = NewTpl;
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//
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// If lowering below HIGH_LEVEL, make sure
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// interrupts are enabled
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//
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if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {
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CoreSetInterruptState (TRUE);
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}
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}
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