d269095b71
In the former memory model, the UEFI firmware was expected to be located at the top of the system memory. Stacks & Pi memory regions were set below the firmware. On some platform, the UEFI firmware could be shadowed by the ROM firmware (case of the BeagleBoard) and in some cases the firmware is copied at the beginning of the system memory. With this new memory model, stack and Pi/DXE memory regions are set at the top of the system memory wherever the UEFI firmware is located in the memory map. Because DXE core does not support shadowed firmwares, the system memory covered by the UEFI firmware is marked as 'Non Present' to avoid to be overlapped by DXE allocations. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11992 6f19259b-4bc3-4df7-8a09-765794883524
68 lines
2.0 KiB
C
68 lines
2.0 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include "PrePi.h"
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#include <Library/ArmMPCoreMailBoxLib.h>
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#include <Chipset/ArmV7.h>
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#include <Drivers/PL390Gic.h>
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VOID
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PrimaryMain (
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IN UINTN UefiMemoryBase,
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IN UINT64 StartTimeStamp
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)
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{
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//Enable the GIC Distributor
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PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
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// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization
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if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {
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// Sending SGI to all the Secondary CPU interfaces
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PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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}
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PrePiMain (UefiMemoryBase, StartTimeStamp);
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// We must never return
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ASSERT(FALSE);
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}
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VOID
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SecondaryMain (
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IN UINTN CoreId
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)
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{
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// Function pointer to Secondary Core entry point
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VOID (*secondary_start)(VOID);
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UINTN secondary_entry_addr=0;
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// Clear Secondary cores MailBox
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ArmClearMPCoreMailbox();
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while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
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}
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secondary_start = (VOID (*)())secondary_entry_addr;
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// Jump to secondary core entry point.
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secondary_start();
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// The secondaries shouldn't reach here
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ASSERT(FALSE);
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}
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