81a23a0fee
Remove the references to DuetPkg. Copy the files from revision
ffea0a2ce2 of DuetPkg into
CorebootModulePkg. The components include:
* PciBusNoEnumerationDxe
* PciRootBridgeNoEnumerationDxe
* SataControllerDxe
TEST=Build and run on Galileo Gen2
Change-Id: Id07185f7e226749e5f7c6b6cb427bcef7eac8496
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
226 lines
6.1 KiB
C
226 lines
6.1 KiB
C
/*++
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Copyright (c) 2005 - 2007, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PciBus.h
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Abstract:
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PCI Bus Driver
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Revision History
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--*/
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#ifndef _EFI_PCI_BUS_H
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#define _EFI_PCI_BUS_H
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#include <PiDxe.h>
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#include <Protocol/PciIo.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Protocol/DevicePath.h>
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#include <Protocol/Decompress.h>
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#include <Protocol/UgaIo.h>
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#include <Protocol/LoadedImage.h>
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#include <Protocol/BusSpecificDriverOverride.h>
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#include <Guid/PciOptionRomTable.h>
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#include <IndustryStandard/Pci.h>
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#include <IndustryStandard/Acpi.h>
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#include <IndustryStandard/PeImage.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiDriverEntryPoint.h>
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#include <Library/BaseLib.h>
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#include <Library/UefiLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/ReportStatusCodeLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PeCoffLib.h>
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//
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// Driver Produced Protocol Prototypes
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//
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#define VGABASE1 0x3B0
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#define VGALIMIT1 0x3BB
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#define VGABASE2 0x3C0
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#define VGALIMIT2 0x3DF
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#define ISABASE 0x100
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#define ISALIMIT 0x3FF
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typedef enum {
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PciBarTypeUnknown = 0,
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PciBarTypeIo16,
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PciBarTypeIo32,
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PciBarTypeMem32,
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PciBarTypePMem32,
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PciBarTypeMem64,
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PciBarTypePMem64,
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PciBarTypeIo,
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PciBarTypeMem,
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PciBarTypeMaxType
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} PCI_BAR_TYPE;
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typedef struct {
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UINT64 BaseAddress;
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UINT64 Length;
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UINT64 Alignment;
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PCI_BAR_TYPE BarType;
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BOOLEAN Prefetchable;
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UINT8 MemType;
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UINT8 Offset;
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} PCI_BAR;
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#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p','c','i','o')
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#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
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#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
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#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
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#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
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#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
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#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
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#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
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typedef struct _PCI_IO_DEVICE {
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UINT32 Signature;
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EFI_HANDLE Handle;
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EFI_PCI_IO_PROTOCOL PciIo;
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LIST_ENTRY Link;
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EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
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//
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// PCI configuration space header type
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//
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PCI_TYPE00 Pci;
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//
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// Bus number, Device number, Function number
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//
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UINT8 BusNumber;
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UINT8 DeviceNumber;
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UINT8 FunctionNumber;
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//
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// BAR for this PCI Device
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//
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PCI_BAR PciBar[PCI_MAX_BAR];
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//
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// The bridge device this pci device is subject to
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//
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struct _PCI_IO_DEVICE *Parent;
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//
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// A linked list for children Pci Device if it is bridge device
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//
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LIST_ENTRY ChildList;
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//
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// TURE if the PCI bus driver creates the handle for this PCI device
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//
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BOOLEAN Registered;
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//
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// TRUE if the PCI bus driver successfully allocates the resource required by
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// this PCI device
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//
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BOOLEAN Allocated;
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//
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// The attribute this PCI device currently set
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//
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UINT64 Attributes;
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//
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// The attributes this PCI device actually supports
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//
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UINT64 Supports;
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//
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// The resource decode the bridge supports
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//
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UINT32 Decodes;
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//
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// The OptionRom Size
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//
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UINT64 RomSize;
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//
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// TRUE if there is any EFI driver in the OptionRom
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//
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BOOLEAN BusOverride;
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//
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// A list tracking reserved resource on a bridge device
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//
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LIST_ENTRY ReservedResourceList;
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//
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// A list tracking image handle of platform specific overriding driver
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//
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LIST_ENTRY OptionRomDriverList;
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BOOLEAN IsPciExp;
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} PCI_IO_DEVICE;
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#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
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CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
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#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
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CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
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#define PCI_IO_DEVICE_FROM_LINK(a) \
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CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
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//
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// Global Variables
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//
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extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
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extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
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extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
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extern BOOLEAN gFullEnumeration;
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extern UINT64 gAllOne;
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extern UINT64 gAllZero;
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#include "PciIo.h"
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#include "PciCommand.h"
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#include "PciDeviceSupport.h"
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#include "PciEnumerator.h"
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#include "PciEnumeratorSupport.h"
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#include "PciDriverOverride.h"
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#include "PciRomTable.h"
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#include "PciOptionRomSupport.h"
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#include "PciPowerManagement.h"
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#define IS_ISA_BRIDGE(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
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#define IS_INTEL_ISA_BRIDGE(_p) (IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE) && ((_p)->Hdr.VendorId == 0x8086) && ((_p)->Hdr.DeviceId == 0x7110))
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#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
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#endif
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