7750468c37
Added LoongArch exception handler into CpuExceptionHandlerLib. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
367 lines
11 KiB
ArmAsm
367 lines
11 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# LoongArch64 ASM exception handler
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#
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# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <Library/BaseLib.h>
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#include <Library/CpuLib.h>
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#include <Register/LoongArch64/Csr.h>
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#define RSIZE 8 // 64 bit mode register size
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#define GP_REG_CONTEXT_SIZE 32 * RSIZE // General-purpose registers size
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#define FP_REG_CONTEXT_SIZE 34 * RSIZE // Floating-point registers size
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#define CSR_REG_CONTEXT_SIZE 9 * RSIZE // CSR registers size
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ASM_GLOBAL ASM_PFX(ExceptionEntry)
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ASM_GLOBAL ASM_PFX(ExceptionEntryStart)
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ASM_GLOBAL ASM_PFX(ExceptionEntryEnd)
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ASM_PFX(ExceptionEntry):
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move $s0, $a0
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bl GetExceptionType // Exception type stored in register a0
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move $a1, $s0 // SystemContxt
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bl CommonExceptionHandler
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PopContext:
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//
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// Not sure if interrupts are turned on during the exception handler, anyway disable interrupts here.
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// It will be turned on when the instruction 'ertn' is executed.
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//
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bl DisableInterrupts
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bl GetExceptionType // Get current exception type, and stored in register a0
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// Check whether the FPE is changed during interrupt handler, if ture restore it.
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ld.d $t1, $sp, (LOONGARCH_CSR_EUEN * RSIZE + GP_REG_CONTEXT_SIZE)
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csrrd $t0, LOONGARCH_CSR_EUEN // Current EUEN
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andi $t0, $t0, CSR_EUEN_FPEN
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andi $t1, $t1, CSR_EUEN_FPEN
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li.d $t2, EXCEPT_LOONGARCH_INT
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bne $a0, $t2, PopRegs
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beq $t0, $t1, PopRegs
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beqz $t1, CloseFP
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bl EnableFloatingPointUnits
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b PopRegs
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CloseFP:
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bl DisableFloatingPointUnits
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PopRegs:
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//
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// Pop CSR reigsters
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//
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addi.d $sp, $sp, GP_REG_CONTEXT_SIZE
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ld.d $t0, $sp, LOONGARCH_CSR_CRMD * RSIZE
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csrwr $t0, LOONGARCH_CSR_CRMD
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ld.d $t0, $sp, LOONGARCH_CSR_PRMD * RSIZE
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csrwr $t0, LOONGARCH_CSR_PRMD
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ld.d $t0, $sp, LOONGARCH_CSR_ECFG * RSIZE
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csrwr $t0, LOONGARCH_CSR_ECFG
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ld.d $t0, $sp, LOONGARCH_CSR_ERA * RSIZE
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csrwr $t0, LOONGARCH_CSR_ERA
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addi.d $sp, $sp, CSR_REG_CONTEXT_SIZE // Fource change the stack pointer befor pop the FP registers.
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beqz $t1, PopGP // If the FPE not set, only pop the GP registers.
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//
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// Pop FP registers
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//
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fld.d $fa0, $sp, 0 * RSIZE
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fld.d $fa1, $sp, 1 * RSIZE
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fld.d $fa2, $sp, 2 * RSIZE
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fld.d $fa3, $sp, 3 * RSIZE
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fld.d $fa4, $sp, 4 * RSIZE
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fld.d $fa5, $sp, 5 * RSIZE
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fld.d $fa6, $sp, 6 * RSIZE
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fld.d $fa7, $sp, 7 * RSIZE
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fld.d $ft0, $sp, 8 * RSIZE
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fld.d $ft1, $sp, 9 * RSIZE
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fld.d $ft2, $sp, 10 * RSIZE
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fld.d $ft3, $sp, 11 * RSIZE
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fld.d $ft4, $sp, 12 * RSIZE
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fld.d $ft5, $sp, 13 * RSIZE
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fld.d $ft6, $sp, 14 * RSIZE
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fld.d $ft7, $sp, 15 * RSIZE
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fld.d $ft8, $sp, 16 * RSIZE
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fld.d $ft9, $sp, 17 * RSIZE
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fld.d $ft10, $sp, 18 * RSIZE
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fld.d $ft11, $sp, 19 * RSIZE
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fld.d $ft12, $sp, 20 * RSIZE
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fld.d $ft13, $sp, 21 * RSIZE
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fld.d $ft14, $sp, 22 * RSIZE
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fld.d $ft15, $sp, 23 * RSIZE
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fld.d $fs0, $sp, 24 * RSIZE
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fld.d $fs1, $sp, 25 * RSIZE
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fld.d $fs2, $sp, 26 * RSIZE
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fld.d $fs3, $sp, 27 * RSIZE
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fld.d $fs4, $sp, 28 * RSIZE
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fld.d $fs5, $sp, 29 * RSIZE
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fld.d $fs6, $sp, 30 * RSIZE
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fld.d $fs7, $sp, 31 * RSIZE
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ld.d $t0, $sp, 32 * RSIZE
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movgr2fcsr $r0, $t0 // Pop the fcsr0 register.
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//
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// Pop the fcc0-fcc7 registers.
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//
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ld.d $t0, $sp, 33 * RSIZE
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bstrpick.d $t1, $t0, 7, 0
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movgr2cf $fcc0, $t1
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bstrpick.d $t1, $t0, 15, 8
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movgr2cf $fcc1, $t1
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bstrpick.d $t1, $t0, 23, 16
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movgr2cf $fcc2, $t1
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bstrpick.d $t1, $t0, 31, 24
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movgr2cf $fcc3, $t1
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bstrpick.d $t1, $t0, 39, 32
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movgr2cf $fcc4, $t1
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bstrpick.d $t1, $t0, 47, 40
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movgr2cf $fcc5, $t1
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bstrpick.d $t1, $t0, 55, 48
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movgr2cf $fcc6, $t1
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bstrpick.d $t1, $t0, 63, 56
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movgr2cf $fcc7, $t1
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PopGP:
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//
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// Pop GP registers
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//
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addi.d $sp, $sp, -(GP_REG_CONTEXT_SIZE + CSR_REG_CONTEXT_SIZE)
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ld.d $ra, $sp, 1 * RSIZE
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ld.d $tp, $sp, 2 * RSIZE
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ld.d $a0, $sp, 4 * RSIZE
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ld.d $a1, $sp, 5 * RSIZE
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ld.d $a2, $sp, 6 * RSIZE
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ld.d $a3, $sp, 7 * RSIZE
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ld.d $a4, $sp, 8 * RSIZE
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ld.d $a5, $sp, 9 * RSIZE
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ld.d $a6, $sp, 10 * RSIZE
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ld.d $a7, $sp, 11 * RSIZE
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ld.d $t0, $sp, 12 * RSIZE
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ld.d $t1, $sp, 13 * RSIZE
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ld.d $t2, $sp, 14 * RSIZE
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ld.d $t3, $sp, 15 * RSIZE
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ld.d $t4, $sp, 16 * RSIZE
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ld.d $t5, $sp, 17 * RSIZE
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ld.d $t6, $sp, 18 * RSIZE
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ld.d $t7, $sp, 19 * RSIZE
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ld.d $t8, $sp, 20 * RSIZE
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ld.d $r21, $sp, 21 * RSIZE
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ld.d $fp, $sp, 22 * RSIZE
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ld.d $s0, $sp, 23 * RSIZE
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ld.d $s1, $sp, 24 * RSIZE
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ld.d $s2, $sp, 25 * RSIZE
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ld.d $s3, $sp, 26 * RSIZE
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ld.d $s4, $sp, 27 * RSIZE
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ld.d $s5, $sp, 28 * RSIZE
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ld.d $s6, $sp, 29 * RSIZE
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ld.d $s7, $sp, 30 * RSIZE
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ld.d $s8, $sp, 31 * RSIZE
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ld.d $sp, $sp, 3 * RSIZE
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ertn // Returen from exception.
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//
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// End of ExceptionEntry
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//
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ASM_PFX(ExceptionEntryStart):
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//
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// Store the old stack pointer in preparation for pushing the exception context onto the new stack.
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//
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csrwr $sp, LOONGARCH_CSR_KS0
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csrrd $sp, LOONGARCH_CSR_KS0
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//
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// Push GP registers
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//
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addi.d $sp, $sp, -(GP_REG_CONTEXT_SIZE + FP_REG_CONTEXT_SIZE + CSR_REG_CONTEXT_SIZE)
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st.d $zero, $sp, 0 * RSIZE
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st.d $ra, $sp, 1 * RSIZE
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st.d $tp, $sp, 2 * RSIZE
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st.d $a0, $sp, 4 * RSIZE
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st.d $a1, $sp, 5 * RSIZE
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st.d $a2, $sp, 6 * RSIZE
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st.d $a3, $sp, 7 * RSIZE
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st.d $a4, $sp, 8 * RSIZE
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st.d $a5, $sp, 9 * RSIZE
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st.d $a6, $sp, 10 * RSIZE
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st.d $a7, $sp, 11 * RSIZE
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st.d $t0, $sp, 12 * RSIZE
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st.d $t1, $sp, 13 * RSIZE
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st.d $t2, $sp, 14 * RSIZE
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st.d $t3, $sp, 15 * RSIZE
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st.d $t4, $sp, 16 * RSIZE
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st.d $t5, $sp, 17 * RSIZE
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st.d $t6, $sp, 18 * RSIZE
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st.d $t7, $sp, 19 * RSIZE
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st.d $t8, $sp, 20 * RSIZE
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st.d $r21, $sp, 21 * RSIZE
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st.d $fp, $sp, 22 * RSIZE
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st.d $s0, $sp, 23 * RSIZE
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st.d $s1, $sp, 24 * RSIZE
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st.d $s2, $sp, 25 * RSIZE
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st.d $s3, $sp, 26 * RSIZE
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st.d $s4, $sp, 27 * RSIZE
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st.d $s5, $sp, 28 * RSIZE
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st.d $s6, $sp, 29 * RSIZE
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st.d $s7, $sp, 30 * RSIZE
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st.d $s8, $sp, 31 * RSIZE
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csrrd $t0, LOONGARCH_CSR_KS0 // Read the old stack pointer.
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st.d $t0, $sp, 3 * RSIZE
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//
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// Push CSR registers
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//
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addi.d $sp, $sp, GP_REG_CONTEXT_SIZE
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csrrd $t0, LOONGARCH_CSR_CRMD
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st.d $t0, $sp, LOONGARCH_CSR_CRMD * RSIZE
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csrrd $t0, LOONGARCH_CSR_PRMD
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st.d $t0, $sp, LOONGARCH_CSR_PRMD * RSIZE
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csrrd $t0, LOONGARCH_CSR_EUEN
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st.d $t0, $sp, LOONGARCH_CSR_EUEN * RSIZE
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csrrd $t0, LOONGARCH_CSR_MISC
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st.d $t0, $sp, LOONGARCH_CSR_MISC * RSIZE
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csrrd $t0, LOONGARCH_CSR_ECFG
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st.d $t0, $sp, LOONGARCH_CSR_ECFG * RSIZE
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csrrd $t0, LOONGARCH_CSR_ESTAT
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st.d $t0, $sp, LOONGARCH_CSR_ESTAT * RSIZE
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csrrd $t0, LOONGARCH_CSR_ERA
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st.d $t0, $sp, LOONGARCH_CSR_ERA * RSIZE
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csrrd $t0, LOONGARCH_CSR_BADV
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st.d $t0, $sp, LOONGARCH_CSR_BADV * RSIZE
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csrrd $t0, LOONGARCH_CSR_BADI
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st.d $t0, $sp, LOONGARCH_CSR_BADI * RSIZE
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//
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// Push FP registers
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//
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addi.d $sp, $sp, CSR_REG_CONTEXT_SIZE
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csrrd $t0, LOONGARCH_CSR_EUEN
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andi $t0, $t0, CSR_EUEN_FPEN
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beqz $t0, PushRegDone
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fst.d $fa0, $sp, 0 * RSIZE
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fst.d $fa1, $sp, 1 * RSIZE
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fst.d $fa2, $sp, 2 * RSIZE
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fst.d $fa3, $sp, 3 * RSIZE
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fst.d $fa4, $sp, 4 * RSIZE
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fst.d $fa5, $sp, 5 * RSIZE
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fst.d $fa6, $sp, 6 * RSIZE
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fst.d $fa7, $sp, 7 * RSIZE
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fst.d $ft0, $sp, 8 * RSIZE
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fst.d $ft1, $sp, 9 * RSIZE
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fst.d $ft2, $sp, 10 * RSIZE
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fst.d $ft3, $sp, 11 * RSIZE
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fst.d $ft4, $sp, 12 * RSIZE
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fst.d $ft5, $sp, 13 * RSIZE
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fst.d $ft6, $sp, 14 * RSIZE
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fst.d $ft7, $sp, 15 * RSIZE
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fst.d $ft8, $sp, 16 * RSIZE
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fst.d $ft9, $sp, 17 * RSIZE
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fst.d $ft10, $sp, 18 * RSIZE
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fst.d $ft11, $sp, 19 * RSIZE
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fst.d $ft12, $sp, 20 * RSIZE
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fst.d $ft13, $sp, 21 * RSIZE
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fst.d $ft14, $sp, 22 * RSIZE
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fst.d $ft15, $sp, 23 * RSIZE
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fst.d $fs0, $sp, 24 * RSIZE
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fst.d $fs1, $sp, 25 * RSIZE
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fst.d $fs2, $sp, 26 * RSIZE
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fst.d $fs3, $sp, 27 * RSIZE
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fst.d $fs4, $sp, 28 * RSIZE
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fst.d $fs5, $sp, 29 * RSIZE
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fst.d $fs6, $sp, 30 * RSIZE
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fst.d $fs7, $sp, 31 * RSIZE
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movfcsr2gr $t3, $r0
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st.d $t3, $sp, 32 * RSIZE // Push the FCSR0 register.
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//
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// Push the fcc0-fcc7 registers.
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//
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movcf2gr $t3, $fcc0
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or $t2, $t3, $zero
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movcf2gr $t3, $fcc1
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bstrins.d $t2, $t3, 0xf, 0x8
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movcf2gr $t3, $fcc2
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bstrins.d $t2, $t3, 0x17, 0x10
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movcf2gr $t3, $fcc3
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bstrins.d $t2, $t3, 0x1f, 0x18
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movcf2gr $t3, $fcc4
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bstrins.d $t2, $t3, 0x27, 0x20
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movcf2gr $t3, $fcc5
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bstrins.d $t2, $t3, 0x2f, 0x28
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movcf2gr $t3, $fcc6
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bstrins.d $t2, $t3, 0x37, 0x30
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movcf2gr $t3, $fcc7
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bstrins.d $t2, $t3, 0x3f, 0x38
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st.d $t2, $sp, 33 * RSIZE
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//
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// Push exception context down
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//
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PushRegDone:
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//
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// Process IPI only when mailbox3 is NULL and mailbox0 is no-NULL.
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//
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li.d $t0, LOONGARCH_IOCSR_MBUF0
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iocsrrd.d $a0, $t0
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beqz $a0, EntryConmmonHanlder
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li.d $t0, LOONGARCH_IOCSR_MBUF3
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iocsrrd.d $t1, $t0
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bnez $t1, EntryConmmonHanlder
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csrrd $t0, LOONGARCH_CSR_ESTAT
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srli.d $t0, $t0, 12
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andi $t0, $t0, 0x1
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beqz $t0, EntryConmmonHanlder
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//
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// Clean up current processor mailbox 0 and mailbox 3.
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//
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li.d $t0, LOONGARCH_IOCSR_MBUF0
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iocsrwr.d $zero, $t0
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li.d $t0, LOONGARCH_IOCSR_MBUF3
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iocsrwr.d $zero, $t0
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//
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// Clear IPI interrupt.
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//
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li.d $t0, LOONGARCH_IOCSR_IPI_STATUS
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iocsrrd.w $t1, $t0
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li.d $t0, LOONGARCH_IOCSR_IPI_CLEAR
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iocsrwr.w $t1, $t0
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//
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// Only kernel stage BSP calls IPI without parameters. Clean up the PIE and make sure
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// global interrupts are turned off for the current processor when jumping to the kernel.
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//
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csrwr $a0, LOONGARCH_CSR_ERA // Update ERA
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li.w $t0, BIT2 // IE
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csrxchg $zero, $t0, LOONGARCH_CSR_PRMD // Clean PIE
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//
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// Return this exception and jump to kernel using ERA.
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//
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ertn
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EntryConmmonHanlder:
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addi.d $sp, $sp, -(GP_REG_CONTEXT_SIZE + CSR_REG_CONTEXT_SIZE)
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move $a0, $sp
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la.abs $ra, ExceptionEntry
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jirl $zero, $ra, 0
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ASM_PFX(ExceptionEntryEnd):
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.end
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