032830e968
Add a new base library named CpuMmuLib and add a LoongArch64 instance with in the library. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn> Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn> Co-authored-by: Xianglai Li <lixianglai@loongson.cn> Co-authored-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Ray Ni <ray.ni@intel.com>
25 lines
694 B
ArmAsm
25 lines
694 B
ArmAsm
#------------------------------------------------------------------------------
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#
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# Invalid TLB operation function
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#
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# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#-----------------------------------------------------------------------------
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#include <Register/LoongArch64/Csr.h>
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ASM_GLOBAL ASM_PFX(InvalidTlb)
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#
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# Invalid corresponding TLB entries are based on the address given
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# @param a0 The address corresponding to the invalid page table entry
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# @retval none
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#
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ASM_PFX(InvalidTlb):
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invtlb INVTLB_ADDR_GTRUE_OR_ASID, $zero, $a0
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jirl $zero, $ra, 0
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.end
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