9a86fd33e9
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1496 This commit copies the exact 8259InterruptControllerDxe driver from PcAtChipsetPkg to OvmfPkg. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
623 lines
17 KiB
C
623 lines
17 KiB
C
/** @file
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This contains the installation function for the driver.
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Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "8259.h"
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//
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// Global for the Legacy 8259 Protocol that is produced by this driver
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//
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EFI_LEGACY_8259_PROTOCOL mInterrupt8259 = {
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Interrupt8259SetVectorBase,
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Interrupt8259GetMask,
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Interrupt8259SetMask,
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Interrupt8259SetMode,
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Interrupt8259GetVector,
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Interrupt8259EnableIrq,
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Interrupt8259DisableIrq,
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Interrupt8259GetInterruptLine,
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Interrupt8259EndOfInterrupt
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};
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//
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// Global for the handle that the Legacy 8259 Protocol is installed
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//
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EFI_HANDLE m8259Handle = NULL;
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UINT8 mMasterBase = 0xff;
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UINT8 mSlaveBase = 0xff;
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EFI_8259_MODE mMode = Efi8259ProtectedMode;
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UINT16 mProtectedModeMask = 0xffff;
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UINT16 mLegacyModeMask;
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UINT16 mProtectedModeEdgeLevel = 0x0000;
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UINT16 mLegacyModeEdgeLevel;
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//
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// Worker Functions
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//
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/**
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Write to mask and edge/level triggered registers of master and slave PICs.
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@param[in] Mask low byte for master PIC mask register,
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high byte for slave PIC mask register.
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@param[in] EdgeLevel low byte for master PIC edge/level triggered register,
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high byte for slave PIC edge/level triggered register.
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**/
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VOID
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Interrupt8259WriteMask (
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IN UINT16 Mask,
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IN UINT16 EdgeLevel
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)
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{
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IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);
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IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));
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IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) EdgeLevel);
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IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (EdgeLevel >> 8));
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}
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/**
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Read from mask and edge/level triggered registers of master and slave PICs.
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@param[out] Mask low byte for master PIC mask register,
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high byte for slave PIC mask register.
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@param[out] EdgeLevel low byte for master PIC edge/level triggered register,
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high byte for slave PIC edge/level triggered register.
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**/
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VOID
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Interrupt8259ReadMask (
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OUT UINT16 *Mask,
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OUT UINT16 *EdgeLevel
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)
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{
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UINT16 MasterValue;
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UINT16 SlaveValue;
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if (Mask != NULL) {
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MasterValue = IoRead8 (LEGACY_8259_MASK_REGISTER_MASTER);
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SlaveValue = IoRead8 (LEGACY_8259_MASK_REGISTER_SLAVE);
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*Mask = (UINT16) (MasterValue | (SlaveValue << 8));
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}
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if (EdgeLevel != NULL) {
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MasterValue = IoRead8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER);
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SlaveValue = IoRead8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE);
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*EdgeLevel = (UINT16) (MasterValue | (SlaveValue << 8));
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}
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}
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//
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// Legacy 8259 Protocol Interface Functions
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//
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/**
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Sets the base address for the 8259 master and slave PICs.
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@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
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@param[in] MasterBase Interrupt vectors for IRQ0-IRQ7.
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@param[in] SlaveBase Interrupt vectors for IRQ8-IRQ15.
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@retval EFI_SUCCESS The 8259 PIC was programmed successfully.
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@retval EFI_DEVICE_ERROR There was an error while writing to the 8259 PIC.
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**/
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EFI_STATUS
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EFIAPI
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Interrupt8259SetVectorBase (
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IN EFI_LEGACY_8259_PROTOCOL *This,
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IN UINT8 MasterBase,
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IN UINT8 SlaveBase
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)
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{
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UINT8 Mask;
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EFI_TPL OriginalTpl;
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OriginalTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
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//
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// Set vector base for slave PIC
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//
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if (SlaveBase != mSlaveBase) {
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mSlaveBase = SlaveBase;
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//
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// Initialization sequence is needed for setting vector base.
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//
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//
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// Preserve interrtup mask register before initialization sequence
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// because it will be cleared during initialization
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//
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Mask = IoRead8 (LEGACY_8259_MASK_REGISTER_SLAVE);
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//
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// ICW1: cascade mode, ICW4 write required
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//
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IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, 0x11);
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//
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// ICW2: new vector base (must be multiple of 8)
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//
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IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, mSlaveBase);
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//
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// ICW3: slave indentification code must be 2
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//
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IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0x02);
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//
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// ICW4: fully nested mode, non-buffered mode, normal EOI, IA processor
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//
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IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0x01);
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//
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// Restore interrupt mask register
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//
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IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, Mask);
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}
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//
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// Set vector base for master PIC
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//
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if (MasterBase != mMasterBase) {
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mMasterBase = MasterBase;
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//
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// Initialization sequence is needed for setting vector base.
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//
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//
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// Preserve interrtup mask register before initialization sequence
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// because it will be cleared during initialization
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//
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Mask = IoRead8 (LEGACY_8259_MASK_REGISTER_MASTER);
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//
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// ICW1: cascade mode, ICW4 write required
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//
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IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, 0x11);
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//
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// ICW2: new vector base (must be multiple of 8)
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//
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IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, mMasterBase);
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//
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// ICW3: slave PIC is cascaded on IRQ2
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//
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IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0x04);
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//
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// ICW4: fully nested mode, non-buffered mode, normal EOI, IA processor
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//
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IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0x01);
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//
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// Restore interrupt mask register
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//
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IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, Mask);
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}
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IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, LEGACY_8259_EOI);
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IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, LEGACY_8259_EOI);
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gBS->RestoreTPL (OriginalTpl);
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return EFI_SUCCESS;
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}
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/**
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Gets the current 16-bit real mode and 32-bit protected-mode IRQ masks.
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@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
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@param[out] LegacyMask 16-bit mode interrupt mask for IRQ0-IRQ15.
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@param[out] LegacyEdgeLevel 16-bit mode edge/level mask for IRQ-IRQ15.
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@param[out] ProtectedMask 32-bit mode interrupt mask for IRQ0-IRQ15.
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@param[out] ProtectedEdgeLevel 32-bit mode edge/level mask for IRQ0-IRQ15.
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@retval EFI_SUCCESS The 8259 PIC was programmed successfully.
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@retval EFI_DEVICE_ERROR There was an error while reading the 8259 PIC.
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**/
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EFI_STATUS
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EFIAPI
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Interrupt8259GetMask (
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IN EFI_LEGACY_8259_PROTOCOL *This,
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OUT UINT16 *LegacyMask, OPTIONAL
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OUT UINT16 *LegacyEdgeLevel, OPTIONAL
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OUT UINT16 *ProtectedMask, OPTIONAL
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OUT UINT16 *ProtectedEdgeLevel OPTIONAL
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)
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{
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if (LegacyMask != NULL) {
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*LegacyMask = mLegacyModeMask;
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}
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if (LegacyEdgeLevel != NULL) {
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*LegacyEdgeLevel = mLegacyModeEdgeLevel;
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}
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if (ProtectedMask != NULL) {
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*ProtectedMask = mProtectedModeMask;
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}
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if (ProtectedEdgeLevel != NULL) {
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*ProtectedEdgeLevel = mProtectedModeEdgeLevel;
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}
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return EFI_SUCCESS;
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}
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/**
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Sets the current 16-bit real mode and 32-bit protected-mode IRQ masks.
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@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
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@param[in] LegacyMask 16-bit mode interrupt mask for IRQ0-IRQ15.
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@param[in] LegacyEdgeLevel 16-bit mode edge/level mask for IRQ-IRQ15.
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@param[in] ProtectedMask 32-bit mode interrupt mask for IRQ0-IRQ15.
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@param[in] ProtectedEdgeLevel 32-bit mode edge/level mask for IRQ0-IRQ15.
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@retval EFI_SUCCESS The 8259 PIC was programmed successfully.
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@retval EFI_DEVICE_ERROR There was an error while writing the 8259 PIC.
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**/
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EFI_STATUS
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EFIAPI
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Interrupt8259SetMask (
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IN EFI_LEGACY_8259_PROTOCOL *This,
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IN UINT16 *LegacyMask, OPTIONAL
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IN UINT16 *LegacyEdgeLevel, OPTIONAL
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IN UINT16 *ProtectedMask, OPTIONAL
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IN UINT16 *ProtectedEdgeLevel OPTIONAL
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)
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{
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if (LegacyMask != NULL) {
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mLegacyModeMask = *LegacyMask;
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}
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if (LegacyEdgeLevel != NULL) {
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mLegacyModeEdgeLevel = *LegacyEdgeLevel;
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}
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if (ProtectedMask != NULL) {
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mProtectedModeMask = *ProtectedMask;
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}
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if (ProtectedEdgeLevel != NULL) {
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mProtectedModeEdgeLevel = *ProtectedEdgeLevel;
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}
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return EFI_SUCCESS;
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}
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/**
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Sets the mode of the PICs.
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@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
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@param[in] Mode 16-bit real or 32-bit protected mode.
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@param[in] Mask The value with which to set the interrupt mask.
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@param[in] EdgeLevel The value with which to set the edge/level mask.
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@retval EFI_SUCCESS The mode was set successfully.
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@retval EFI_INVALID_PARAMETER The mode was not set.
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**/
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EFI_STATUS
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EFIAPI
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Interrupt8259SetMode (
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IN EFI_LEGACY_8259_PROTOCOL *This,
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IN EFI_8259_MODE Mode,
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IN UINT16 *Mask, OPTIONAL
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IN UINT16 *EdgeLevel OPTIONAL
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)
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{
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if (Mode == mMode) {
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return EFI_SUCCESS;
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}
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if (Mode == Efi8259LegacyMode) {
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//
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// In Efi8259ProtectedMode, mask and edge/level trigger registers should
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// be changed through this protocol, so we can track them in the
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// corresponding module variables.
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//
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Interrupt8259ReadMask (&mProtectedModeMask, &mProtectedModeEdgeLevel);
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if (Mask != NULL) {
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//
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// Update the Mask for the new mode
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//
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mLegacyModeMask = *Mask;
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}
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if (EdgeLevel != NULL) {
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//
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// Update the Edge/Level triggered mask for the new mode
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//
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mLegacyModeEdgeLevel = *EdgeLevel;
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}
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mMode = Mode;
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//
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// Write new legacy mode mask/trigger level
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//
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Interrupt8259WriteMask (mLegacyModeMask, mLegacyModeEdgeLevel);
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return EFI_SUCCESS;
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}
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if (Mode == Efi8259ProtectedMode) {
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//
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// Save the legacy mode mask/trigger level
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//
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Interrupt8259ReadMask (&mLegacyModeMask, &mLegacyModeEdgeLevel);
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//
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// Always force Timer to be enabled after return from 16-bit code.
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// This always insures that on next entry, timer is counting.
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//
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mLegacyModeMask &= 0xFFFE;
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if (Mask != NULL) {
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//
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// Update the Mask for the new mode
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//
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mProtectedModeMask = *Mask;
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}
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if (EdgeLevel != NULL) {
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//
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// Update the Edge/Level triggered mask for the new mode
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//
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mProtectedModeEdgeLevel = *EdgeLevel;
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}
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mMode = Mode;
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//
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// Write new protected mode mask/trigger level
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//
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Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);
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return EFI_SUCCESS;
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}
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return EFI_INVALID_PARAMETER;
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}
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/**
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Translates the IRQ into a vector.
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@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
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@param[in] Irq IRQ0-IRQ15.
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@param[out] Vector The vector that is assigned to the IRQ.
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@retval EFI_SUCCESS The Vector that matches Irq was returned.
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@retval EFI_INVALID_PARAMETER Irq is not valid.
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**/
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EFI_STATUS
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EFIAPI
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Interrupt8259GetVector (
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IN EFI_LEGACY_8259_PROTOCOL *This,
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IN EFI_8259_IRQ Irq,
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OUT UINT8 *Vector
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)
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{
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if ((UINT32)Irq > Efi8259Irq15) {
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return EFI_INVALID_PARAMETER;
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}
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if (Irq <= Efi8259Irq7) {
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*Vector = (UINT8) (mMasterBase + Irq);
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} else {
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*Vector = (UINT8) (mSlaveBase + (Irq - Efi8259Irq8));
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}
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return EFI_SUCCESS;
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}
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/**
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Enables the specified IRQ.
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@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
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@param[in] Irq IRQ0-IRQ15.
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@param[in] LevelTriggered 0 = Edge triggered; 1 = Level triggered.
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@retval EFI_SUCCESS The Irq was enabled on the 8259 PIC.
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@retval EFI_INVALID_PARAMETER The Irq is not valid.
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**/
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EFI_STATUS
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EFIAPI
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Interrupt8259EnableIrq (
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IN EFI_LEGACY_8259_PROTOCOL *This,
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IN EFI_8259_IRQ Irq,
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IN BOOLEAN LevelTriggered
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)
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{
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if ((UINT32)Irq > Efi8259Irq15) {
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return EFI_INVALID_PARAMETER;
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}
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mProtectedModeMask = (UINT16) (mProtectedModeMask & ~(1 << Irq));
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if (LevelTriggered) {
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mProtectedModeEdgeLevel = (UINT16) (mProtectedModeEdgeLevel | (1 << Irq));
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} else {
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mProtectedModeEdgeLevel = (UINT16) (mProtectedModeEdgeLevel & ~(1 << Irq));
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}
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Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);
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return EFI_SUCCESS;
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}
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/**
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Disables the specified IRQ.
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@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
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@param[in] Irq IRQ0-IRQ15.
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@retval EFI_SUCCESS The Irq was disabled on the 8259 PIC.
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@retval EFI_INVALID_PARAMETER The Irq is not valid.
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**/
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EFI_STATUS
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EFIAPI
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Interrupt8259DisableIrq (
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IN EFI_LEGACY_8259_PROTOCOL *This,
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IN EFI_8259_IRQ Irq
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)
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{
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if ((UINT32)Irq > Efi8259Irq15) {
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return EFI_INVALID_PARAMETER;
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}
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mProtectedModeMask = (UINT16) (mProtectedModeMask | (1 << Irq));
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mProtectedModeEdgeLevel = (UINT16) (mProtectedModeEdgeLevel & ~(1 << Irq));
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Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);
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return EFI_SUCCESS;
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}
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/**
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Reads the PCI configuration space to get the interrupt number that is assigned to the card.
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@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
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@param[in] PciHandle PCI function for which to return the vector.
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@param[out] Vector IRQ number that corresponds to the interrupt line.
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@retval EFI_SUCCESS The interrupt line value was read successfully.
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**/
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EFI_STATUS
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EFIAPI
|
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Interrupt8259GetInterruptLine (
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IN EFI_LEGACY_8259_PROTOCOL *This,
|
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IN EFI_HANDLE PciHandle,
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OUT UINT8 *Vector
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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UINT8 InterruptLine;
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EFI_STATUS Status;
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Status = gBS->HandleProtocol (
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PciHandle,
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&gEfiPciIoProtocolGuid,
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(VOID **) &PciIo
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);
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if (EFI_ERROR (Status)) {
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return EFI_INVALID_PARAMETER;
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}
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|
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint8,
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PCI_INT_LINE_OFFSET,
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1,
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&InterruptLine
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);
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//
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// Interrupt line is same location for standard PCI cards, standard
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// bridge and CardBus bridge.
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//
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*Vector = InterruptLine;
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Issues the End of Interrupt (EOI) commands to PICs.
|
|
|
|
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
|
|
@param[in] Irq The interrupt for which to issue the EOI command.
|
|
|
|
@retval EFI_SUCCESS The EOI command was issued.
|
|
@retval EFI_INVALID_PARAMETER The Irq is not valid.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
Interrupt8259EndOfInterrupt (
|
|
IN EFI_LEGACY_8259_PROTOCOL *This,
|
|
IN EFI_8259_IRQ Irq
|
|
)
|
|
{
|
|
if ((UINT32)Irq > Efi8259Irq15) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
if (Irq >= Efi8259Irq8) {
|
|
IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, LEGACY_8259_EOI);
|
|
}
|
|
|
|
IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, LEGACY_8259_EOI);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Driver Entry point.
|
|
|
|
@param[in] ImageHandle ImageHandle of the loaded driver.
|
|
@param[in] SystemTable Pointer to the EFI System Table.
|
|
|
|
@retval EFI_SUCCESS One or more of the drivers returned a success code.
|
|
@retval !EFI_SUCCESS Error installing Legacy 8259 Protocol.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
Install8259 (
|
|
IN EFI_HANDLE ImageHandle,
|
|
IN EFI_SYSTEM_TABLE *SystemTable
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
EFI_8259_IRQ Irq;
|
|
|
|
//
|
|
// Initialze mask values from PCDs
|
|
//
|
|
mLegacyModeMask = PcdGet16 (Pcd8259LegacyModeMask);
|
|
mLegacyModeEdgeLevel = PcdGet16 (Pcd8259LegacyModeEdgeLevel);
|
|
|
|
//
|
|
// Clear all pending interrupt
|
|
//
|
|
for (Irq = Efi8259Irq0; Irq <= Efi8259Irq15; Irq++) {
|
|
Interrupt8259EndOfInterrupt (&mInterrupt8259, Irq);
|
|
}
|
|
|
|
//
|
|
// Set the 8259 Master base to 0x68 and the 8259 Slave base to 0x70
|
|
//
|
|
Status = Interrupt8259SetVectorBase (&mInterrupt8259, PROTECTED_MODE_BASE_VECTOR_MASTER, PROTECTED_MODE_BASE_VECTOR_SLAVE);
|
|
|
|
//
|
|
// Set all 8259 interrupts to edge triggered and disabled
|
|
//
|
|
Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);
|
|
|
|
//
|
|
// Install 8259 Protocol onto a new handle
|
|
//
|
|
Status = gBS->InstallProtocolInterface (
|
|
&m8259Handle,
|
|
&gEfiLegacy8259ProtocolGuid,
|
|
EFI_NATIVE_INTERFACE,
|
|
&mInterrupt8259
|
|
);
|
|
return Status;
|
|
}
|