d4d87596c1
If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory of EfiBootServicesCode, EfiConventionalMemory, the BIOS will hang at a page fault exception triggered by PiSmmCpuDxeSmm. The root cause is that PiSmmCpuDxeSmm will access default SMM RAM starting at 0x30000 which is marked as non-executable, but NX feature was not enabled during SMM initialization. Accessing memory which has invalid attributes set will cause page fault exception. This patch fixes it by checking NX capability in cpuid and enable NXE in EFER MSR if it's available. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
152 lines
4.5 KiB
NASM
152 lines
4.5 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmmInit.nasm
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;
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; Abstract:
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;
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; Functions for relocating SMBASE's for all processors
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;
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;-------------------------------------------------------------------------------
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extern ASM_PFX(SmmInitHandler)
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extern ASM_PFX(mRebasedFlag)
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extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gSmmCr3)
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global ASM_PFX(gSmmCr4)
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global ASM_PFX(gSmmCr0)
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global ASM_PFX(gSmmJmpAddr)
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global ASM_PFX(gSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitTemplate)
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global ASM_PFX(mRebasedFlagAddr32)
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global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
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DEFAULT REL
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SECTION .text
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ASM_PFX(gcSmiInitGdtr):
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DW 0
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DQ 0
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global ASM_PFX(SmmStartup)
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ASM_PFX(SmmStartup):
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DB 0x66
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mov eax, 0x80000001 ; read capability
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cpuid
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DB 0x66
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mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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DB 0x66, 0xb8 ; mov eax, imm32
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ASM_PFX(gSmmCr3): DD 0
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mov cr3, rax
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DB 0x66, 0x2e
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lgdt [ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
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DB 0x66, 0xb8 ; mov eax, imm32
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ASM_PFX(gSmmCr4): DD 0
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or ah, 2 ; enable XMM registers access
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mov cr4, rax
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DB 0x66
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mov ecx, 0xc0000080 ; IA32_EFER MSR
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rdmsr
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or ah, BIT0 ; set LME bit
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DB 0x66
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test ebx, BIT20 ; check NXE capability
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jz .1
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or ah, BIT3 ; set NXE bit
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.1:
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wrmsr
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DB 0x66, 0xb8 ; mov eax, imm32
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ASM_PFX(gSmmCr0): DD 0
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mov cr0, rax ; enable protected mode & paging
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DB 0x66, 0xea ; far jmp to long mode
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ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
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@LongMode: ; long-mode starts here
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DB 0x48, 0xbc ; mov rsp, imm64
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ASM_PFX(gSmmInitStack): DQ 0
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and sp, 0xfff0 ; make sure RSP is 16-byte aligned
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;
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; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
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; them before calling C-function.
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;
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sub rsp, 0x60
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movdqa [rsp], xmm0
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movdqa [rsp + 0x10], xmm1
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movdqa [rsp + 0x20], xmm2
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movdqa [rsp + 0x30], xmm3
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movdqa [rsp + 0x40], xmm4
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movdqa [rsp + 0x50], xmm5
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add rsp, -0x20
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call ASM_PFX(SmmInitHandler)
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add rsp, 0x20
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;
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; Restore XMM0~5 after calling C-function.
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;
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movdqa xmm0, [rsp]
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movdqa xmm1, [rsp + 0x10]
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movdqa xmm2, [rsp + 0x20]
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movdqa xmm3, [rsp + 0x30]
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movdqa xmm4, [rsp + 0x40]
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movdqa xmm5, [rsp + 0x50]
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rsm
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BITS 16
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ASM_PFX(gcSmmInitTemplate):
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mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
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sub ebp, 0x30000
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jmp ebp
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@L1:
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DQ 0; ASM_PFX(SmmStartup)
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ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
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BITS 64
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global ASM_PFX(SmmRelocationSemaphoreComplete)
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ASM_PFX(SmmRelocationSemaphoreComplete):
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push rax
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mov rax, [ASM_PFX(mRebasedFlag)]
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mov byte [rax], 1
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pop rax
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jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
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;
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; Semaphore code running in 32-bit mode
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;
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global ASM_PFX(SmmRelocationSemaphoreComplete32)
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ASM_PFX(SmmRelocationSemaphoreComplete32):
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;
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; mov byte ptr [], 1
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;
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db 0xc6, 0x5
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ASM_PFX(mRebasedFlagAddr32): dd 0
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db 1
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;
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; jmp dword ptr []
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;
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db 0xff, 0x25
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ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
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global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
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ASM_PFX(PiSmmCpuSmmInitFixupAddress):
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lea rax, [@LongMode]
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lea rcx, [ASM_PFX(gSmmJmpAddr)]
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mov qword [rcx], rax
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lea rax, [ASM_PFX(SmmStartup)]
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lea rcx, [@L1]
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mov qword [rcx], rax
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ret
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