d5788777bc
Currently, we always invalidate the TLBs entirely after making any modification to the page tables. Now that we have introduced strict memory permissions in quite a number of places, such modifications occur much more often, and it is better for performance to flush only those TLB entries that are actually affected by the changes. At the same time, relax some system wide data synchronization barriers to non-shared. When running in UEFI, we don't share virtual address translations with other masters, unless we are running under virt, but in that case, the host will upgrade them as appropriate (by setting an override at EL2) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
217 lines
5.1 KiB
ArmAsm
217 lines
5.1 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLibV8.h>
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.set DAIF_RD_FIQ_BIT, (1 << 6)
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.set DAIF_RD_IRQ_BIT, (1 << 7)
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ASM_FUNC(ArmReadMidr)
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mrs x0, midr_el1 // Read from Main ID Register (MIDR)
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ret
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ASM_FUNC(ArmCacheInfo)
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mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)
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ret
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ASM_FUNC(ArmGetInterruptState)
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mrs x0, daif
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tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)
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cset w0, eq // if Z=1 return 1, else 0
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ret
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ASM_FUNC(ArmGetFiqState)
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mrs x0, daif
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tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)
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cset w0, eq // if Z=1 return 1, else 0
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ret
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ASM_FUNC(ArmWriteCpacr)
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msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)
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ret
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ASM_FUNC(ArmWriteAuxCr)
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EL1_OR_EL2(x1)
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1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
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ret
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2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
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ret
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ASM_FUNC(ArmReadAuxCr)
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EL1_OR_EL2(x1)
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1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
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ret
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2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
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ret
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ASM_FUNC(ArmSetTTBR0)
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EL1_OR_EL2_OR_EL3(x1)
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1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)
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b 4f
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2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)
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b 4f
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3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)
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4:isb
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ret
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ASM_FUNC(ArmGetTTBR0BaseAddress)
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EL1_OR_EL2(x1)
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1:mrs x0, ttbr0_el1
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b 3f
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2:mrs x0, ttbr0_el2
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3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */
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isb
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ret
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ASM_FUNC(ArmGetTCR)
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EL1_OR_EL2_OR_EL3(x1)
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1:mrs x0, tcr_el1
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b 4f
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2:mrs x0, tcr_el2
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b 4f
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3:mrs x0, tcr_el3
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4:isb
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ret
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ASM_FUNC(ArmSetTCR)
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EL1_OR_EL2_OR_EL3(x1)
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1:msr tcr_el1, x0
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b 4f
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2:msr tcr_el2, x0
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b 4f
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3:msr tcr_el3, x0
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4:isb
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ret
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ASM_FUNC(ArmGetMAIR)
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EL1_OR_EL2_OR_EL3(x1)
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1:mrs x0, mair_el1
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b 4f
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2:mrs x0, mair_el2
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b 4f
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3:mrs x0, mair_el3
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4:isb
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ret
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ASM_FUNC(ArmSetMAIR)
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EL1_OR_EL2_OR_EL3(x1)
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1:msr mair_el1, x0
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b 4f
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2:msr mair_el2, x0
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b 4f
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3:msr mair_el3, x0
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4:isb
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ret
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//
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//VOID
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//ArmUpdateTranslationTableEntry (
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// IN VOID *TranslationTableEntry // X0
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// IN VOID *MVA // X1
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// );
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ASM_FUNC(ArmUpdateTranslationTableEntry)
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dsb nshst
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lsr x1, x1, #12
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EL1_OR_EL2_OR_EL3(x0)
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1: tlbi vaae1, x1 // TLB Invalidate VA , EL1
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b 4f
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2: tlbi vae2, x1 // TLB Invalidate VA , EL2
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b 4f
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3: tlbi vae3, x1 // TLB Invalidate VA , EL3
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4: dsb nsh
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isb
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ret
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ASM_FUNC(ArmInvalidateTlb)
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EL1_OR_EL2_OR_EL3(x0)
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1: tlbi vmalle1
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b 4f
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2: tlbi alle2
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b 4f
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3: tlbi alle3
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4: dsb sy
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isb
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ret
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ASM_FUNC(ArmWriteCptr)
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msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
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ret
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ASM_FUNC(ArmWriteScr)
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msr scr_el3, x0 // Secure configuration register EL3
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isb
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ret
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ASM_FUNC(ArmWriteMVBar)
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msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3
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ret
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ASM_FUNC(ArmCallWFE)
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wfe
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ret
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ASM_FUNC(ArmCallSEV)
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sev
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ret
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ASM_FUNC(ArmReadCpuActlr)
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mrs x0, S3_1_c15_c2_0
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ret
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ASM_FUNC(ArmWriteCpuActlr)
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msr S3_1_c15_c2_0, x0
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dsb sy
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isb
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ret
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ASM_FUNC(ArmReadSctlr)
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EL1_OR_EL2_OR_EL3(x1)
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1:mrs x0, sctlr_el1
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ret
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2:mrs x0, sctlr_el2
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ret
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3:mrs x0, sctlr_el3
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4:ret
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ASM_FUNC(ArmWriteSctlr)
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EL1_OR_EL2_OR_EL3(x1)
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1:msr sctlr_el1, x0
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ret
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2:msr sctlr_el2, x0
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ret
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3:msr sctlr_el3, x0
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4:ret
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ASM_FUNC(ArmGetPhysicalAddressBits)
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mrs x0, id_aa64mmfr0_el1
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adr x1, .LPARanges
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and x0, x0, #0xf
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ldrb w0, [x1, x0]
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ret
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//
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// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the
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// physical address space support on this CPU:
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// 0 == 32 bits, 1 == 36 bits, etc etc
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// 7 and up are reserved
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//
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.LPARanges:
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.byte 32, 36, 40, 42, 44, 48, 52, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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