d5788777bc
Currently, we always invalidate the TLBs entirely after making any modification to the page tables. Now that we have introduced strict memory permissions in quite a number of places, such modifications occur much more often, and it is better for performance to flush only those TLB entries that are actually affected by the changes. At the same time, relax some system wide data synchronization barriers to non-shared. When running in UEFI, we don't share virtual address translations with other masters, unless we are running under virt, but in that case, the host will upgrade them as appropriate (by setting an override at EL2) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
81 lines
2.0 KiB
ArmAsm
81 lines
2.0 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLibV8.h>
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.set CTRL_M_BIT, (1 << 0)
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.macro __replace_entry, el
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// disable the MMU
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mrs x8, sctlr_el\el
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bic x9, x8, #CTRL_M_BIT
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msr sctlr_el\el, x9
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isb
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// write updated entry
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str x1, [x0]
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// invalidate again to get rid of stale clean cachelines that may
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// have been filled speculatively since the last invalidate
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dmb sy
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dc ivac, x0
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// flush translations for the target address from the TLBs
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lsr x2, x2, #12
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.if \el == 1
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tlbi vaae1, x2
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.else
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tlbi vae\el, x2
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.endif
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dsb nsh
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// re-enable the MMU
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msr sctlr_el\el, x8
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isb
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.endm
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//VOID
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//ArmReplaceLiveTranslationEntry (
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// IN UINT64 *Entry,
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// IN UINT64 Value,
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// IN UINT64 Address
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// )
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ASM_FUNC(ArmReplaceLiveTranslationEntry)
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// disable interrupts
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mrs x4, daif
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msr daifset, #0xf
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isb
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// clean and invalidate first so that we don't clobber
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// adjacent entries that are dirty in the caches
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dc civac, x0
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dsb nsh
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EL1_OR_EL2_OR_EL3(x3)
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1:__replace_entry 1
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b 4f
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2:__replace_entry 2
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b 4f
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3:__replace_entry 3
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4:msr daif, x4
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ret
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ASM_GLOBAL ASM_PFX(ArmReplaceLiveTranslationEntrySize)
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ASM_PFX(ArmReplaceLiveTranslationEntrySize):
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.long . - ArmReplaceLiveTranslationEntry
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