d5e064447f
Recognize an extended TSEG when available in
Q35TsegMbytesInitialization(), and set both PcdQ35TsegMbytes (for
OvmfPkg/SmmAccess) and "mQ35TsegMbytes" (for PlatformPei's own use)
accordingly. The new logic interfaces with the QEMU feature added in QEMU
commit 2f295167e0c4 ("q35/mch: implement extended TSEG sizes",
2017-06-08).
At this point we have to explicitly restrict Q35TsegMbytesInitialization()
to the Q35 board, but that's OK, because Q35TsegMbytesInitialization() is
only called when PcdSmmSmramRequire is set, and for that Q35 is already an
enforced requirement.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Suggested-by: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
114 lines
2.0 KiB
C
114 lines
2.0 KiB
C
/** @file
|
|
Platform PEI module include file.
|
|
|
|
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
|
|
This program and the accompanying materials
|
|
are licensed and made available under the terms and conditions of the BSD License
|
|
which accompanies this distribution. The full text of the license may be found at
|
|
http://opensource.org/licenses/bsd-license.php
|
|
|
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
|
|
**/
|
|
|
|
#ifndef _PLATFORM_PEI_H_INCLUDED_
|
|
#define _PLATFORM_PEI_H_INCLUDED_
|
|
|
|
#include <IndustryStandard/E820.h>
|
|
|
|
VOID
|
|
AddIoMemoryBaseSizeHob (
|
|
EFI_PHYSICAL_ADDRESS MemoryBase,
|
|
UINT64 MemorySize
|
|
);
|
|
|
|
VOID
|
|
AddIoMemoryRangeHob (
|
|
EFI_PHYSICAL_ADDRESS MemoryBase,
|
|
EFI_PHYSICAL_ADDRESS MemoryLimit
|
|
);
|
|
|
|
VOID
|
|
AddMemoryBaseSizeHob (
|
|
EFI_PHYSICAL_ADDRESS MemoryBase,
|
|
UINT64 MemorySize
|
|
);
|
|
|
|
VOID
|
|
AddMemoryRangeHob (
|
|
EFI_PHYSICAL_ADDRESS MemoryBase,
|
|
EFI_PHYSICAL_ADDRESS MemoryLimit
|
|
);
|
|
|
|
VOID
|
|
AddReservedMemoryBaseSizeHob (
|
|
EFI_PHYSICAL_ADDRESS MemoryBase,
|
|
UINT64 MemorySize,
|
|
BOOLEAN Cacheable
|
|
);
|
|
|
|
VOID
|
|
AddressWidthInitialization (
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
Q35TsegMbytesInitialization (
|
|
VOID
|
|
);
|
|
|
|
EFI_STATUS
|
|
PublishPeiMemory (
|
|
VOID
|
|
);
|
|
|
|
UINT32
|
|
GetSystemMemorySizeBelow4gb (
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
InitializeRamRegions (
|
|
VOID
|
|
);
|
|
|
|
EFI_STATUS
|
|
PeiFvInitialization (
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
InstallFeatureControlCallback (
|
|
VOID
|
|
);
|
|
|
|
EFI_STATUS
|
|
InitializeXen (
|
|
VOID
|
|
);
|
|
|
|
BOOLEAN
|
|
XenDetect (
|
|
VOID
|
|
);
|
|
|
|
extern BOOLEAN mXen;
|
|
|
|
VOID
|
|
XenPublishRamRegions (
|
|
VOID
|
|
);
|
|
|
|
extern EFI_BOOT_MODE mBootMode;
|
|
|
|
extern BOOLEAN mS3Supported;
|
|
|
|
extern UINT8 mPhysMemAddressWidth;
|
|
|
|
extern UINT32 mMaxCpuCount;
|
|
|
|
extern UINT16 mHostBridgeDevId;
|
|
|
|
#endif // _PLATFORM_PEI_H_INCLUDED_
|