d7b6c49b78
Previously the CPU driver had a dependency on the GIC driver. But by design is should be the opposite. The CPU driver installs the CPU protocol that exposes the exception registration function. And then, the interrupt controller registers its IRQ handler through this interface. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11860 6f19259b-4bc3-4df7-8a09-765794883524
416 lines
12 KiB
C
416 lines
12 KiB
C
/*++
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Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
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Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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Gic.c
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Abstract:
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Driver implementing the GIC interrupt controller protocol
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--*/
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#include <PiDxe.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Protocol/Cpu.h>
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#include <Protocol/HardwareInterrupt.h>
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#include <Drivers/PL390Gic.h>
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// number of 32-bit registers needed to represent those interrupts as a bit
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// (used for enable set, enable clear, pending set, pending clear, and active regs)
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#define GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32)
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// number of 32-bit registers needed to represent those interrupts as two bits
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// (used for configuration reg)
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#define GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16)
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// number of 32-bit registers needed to represent interrupts as 8-bit priority field
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// (used for priority regs)
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#define GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4)
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#define GIC_DEFAULT_PRIORITY 0x80
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
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//
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// Notifications
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//
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EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
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HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[FixedPcdGet32(PcdGicNumInterrupts)];
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/**
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Register Handler for the specified interrupt source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@param Handler Callback for interrupt. NULL to unregister
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@retval EFI_SUCCESS Source was updated to support Handler.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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RegisterInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN HARDWARE_INTERRUPT_HANDLER Handler
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)
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{
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if (Source > PcdGet32(PcdGicNumInterrupts)) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
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return EFI_ALREADY_STARTED;
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}
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gRegisteredInterruptHandlers[Source] = Handler;
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return This->EnableInterruptSource(This, Source);
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}
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/**
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Enable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt enabled.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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EnableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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if (Source > PcdGet32(PcdGicNumInterrupts)) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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// calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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// write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift);
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return EFI_SUCCESS;
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}
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/**
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Disable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt disabled.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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DisableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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if (Source > PcdGet32(PcdGicNumInterrupts)) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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// Write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift);
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return EFI_SUCCESS;
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}
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/**
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Return current state of interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@param InterruptState TRUE: source enabled, FALSE: source disabled.
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@retval EFI_SUCCESS InterruptState is valid
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@retval EFI_DEVICE_ERROR InterruptState is not valid
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**/
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EFI_STATUS
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EFIAPI
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GetInterruptSourceState (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN BOOLEAN *InterruptState
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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if (Source > PcdGet32(PcdGicNumInterrupts)) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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// calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
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*InterruptState = FALSE;
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} else {
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*InterruptState = TRUE;
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}
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return EFI_SUCCESS;
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}
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/**
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Signal to the hardware that the End Of Intrrupt state
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has been reached.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt EOI'ed.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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EndOfInterrupt (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source > PcdGet32(PcdGicNumInterrupts)) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, Source);
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return EFI_SUCCESS;
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}
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/**
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EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
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@param InterruptType Defines the type of interrupt or exception that
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occurred on the processor.This parameter is processor architecture specific.
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@param SystemContext A pointer to the processor context when
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the interrupt occurred on the processor.
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@return None
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**/
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VOID
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EFIAPI
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IrqInterruptHandler (
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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UINT32 GicInterrupt;
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HARDWARE_INTERRUPT_HANDLER InterruptHandler;
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GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCIAR);
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if (GicInterrupt >= PcdGet32(PcdGicNumInterrupts)) {
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, GicInterrupt);
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return;
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}
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InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
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if (InterruptHandler != NULL) {
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// Call the registered interrupt handler.
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InterruptHandler (GicInterrupt, SystemContext);
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} else {
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DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
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}
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EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);
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}
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//
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// Making this global saves a few bytes in image size
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//
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EFI_HANDLE gHardwareInterruptHandle = NULL;
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//
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// The protocol instance produced by this driver
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//
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EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
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RegisterInterruptSource,
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EnableInterruptSource,
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DisableInterruptSource,
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GetInterruptSourceState,
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EndOfInterrupt
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};
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/**
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Shutdown our hardware
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DXE Core will disable interrupts and turn off the timer and disable interrupts
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after all the event handlers have run.
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@param[in] Event The Event that is being processed
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@param[in] Context Event Context
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**/
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VOID
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EFIAPI
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ExitBootServicesEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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UINTN Index;
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for (Index = 0; Index < PcdGet32(PcdGicNumInterrupts); Index++) {
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DisableInterruptSource (&gHardwareInterruptProtocol, Index);
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}
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// Acknowledge all pending interrupts
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for (Index = 0; Index < PcdGet32(PcdGicNumInterrupts); Index++) {
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DisableInterruptSource (&gHardwareInterruptProtocol, Index);
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}
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for (Index = 0; Index < PcdGet32(PcdGicNumInterrupts); Index++) {
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EndOfInterrupt (&gHardwareInterruptProtocol, Index);
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}
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// Disable Gic Interface
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x0);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0x0);
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// Disable Gic Distributor
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x0);
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}
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/**
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Initialize the state information for the CPU Architectural Protocol
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@param ImageHandle of the loaded driver
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@param SystemTable Pointer to the System Table
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@retval EFI_SUCCESS Protocol registered
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@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
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@retval EFI_DEVICE_ERROR Hardware problems
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**/
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EFI_STATUS
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InterruptDxeInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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UINT32 RegOffset;
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UINTN RegShift;
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EFI_CPU_ARCH_PROTOCOL *Cpu;
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// Make sure the Interrupt Controller Protocol is not already installed in the system.
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ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
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for (Index = 0; Index < PcdGet32(PcdGicNumInterrupts); Index++) {
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DisableInterruptSource (&gHardwareInterruptProtocol, Index);
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// Set Priority
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RegOffset = Index / 4;
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RegShift = (Index % 4) * 8;
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MmioAndThenOr32 (
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PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset),
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~(0xff << RegShift),
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GIC_DEFAULT_PRIORITY << RegShift
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);
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}
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// Configure interrupts for cpu 0
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for (Index = 0; Index < GIC_NUM_REG_PER_INT_BYTES; Index++) {
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (Index*4), 0x01010101);
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}
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// Set binary point reg to 0x7 (no preemption)
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7);
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// Set priority mask reg to 0xff to allow all priorities through
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff);
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// Enable gic cpu interface
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1);
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// Enable gic distributor
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1);
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ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));
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Status = gBS->InstallMultipleProtocolInterfaces (
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&gHardwareInterruptHandle,
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&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Get the CPU protocol that this driver requires.
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//
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Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
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ASSERT_EFI_ERROR(Status);
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//
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// Unregister the default exception handler.
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//
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Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
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ASSERT_EFI_ERROR(Status);
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//
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// Register to receive interrupts
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//
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Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
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ASSERT_EFI_ERROR(Status);
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// Register for an ExitBootServicesEvent
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Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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