f4dfad05dd
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
43 lines
1.4 KiB
ArmAsm
43 lines
1.4 KiB
ArmAsm
#========================================================================================
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# Copyright (c) 2011-2017, ARM Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#=======================================================================================
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#include <AsmMacroIoLibV8.h>
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#include <Chipset/AArch64.h>
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// Setup EL1 while in EL1
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ASM_FUNC(SetupExceptionLevel1)
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mov x5, x30 // Save LR
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mov x0, #CPACR_CP_FULL_ACCESS
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bl ASM_PFX(ArmWriteCpacr) // Disable copro traps to EL1
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ret x5
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// Setup EL2 while in EL2
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ASM_FUNC(SetupExceptionLevel2)
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msr sctlr_el2, xzr
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mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
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// Send all interrupts to their respective Exception levels for EL2
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orr x0, x0, #(1 << 3) // Enable EL2 FIQ
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orr x0, x0, #(1 << 4) // Enable EL2 IRQ
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orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort
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msr hcr_el2, x0 // Write back our settings
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msr cptr_el2, xzr // Disable copro traps to EL2
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// Enable Timer access for non-secure EL1 and EL0
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// The cnthctl_el2 register bits are architecturally
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// UNKNOWN on reset.
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// Disable event stream as it is not in use at this stage
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mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)
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msr cnthctl_el2, x0
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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