f4dfad05dd
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
91 lines
2.8 KiB
ArmAsm
91 lines
2.8 KiB
ArmAsm
//
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// Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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#include <AsmMacroIoLibV8.h>
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ASM_FUNC(_ModuleEntryPoint)
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// Do early platform specific actions
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bl ASM_PFX(ArmPlatformPeiBootAction)
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// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
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// and configure the system accordingly. EL2 is default if possible.
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// If we started in EL3 we need to switch and run at EL2.
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// If we are running at EL2 stay in EL2
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// If we are starting at EL1 stay in EL1.
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// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.
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// If started at EL1 or EL2 Sec jumps directly to PEI without making any
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// changes.
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// Which EL are we running at? Every EL needs some level of setup...
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// We should not run this code in EL3
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EL1_OR_EL2(x0)
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1:bl ASM_PFX(SetupExceptionLevel1)
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b ASM_PFX(MainEntryPoint)
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2:bl ASM_PFX(SetupExceptionLevel2)
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b ASM_PFX(MainEntryPoint)
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ASM_PFX(MainEntryPoint):
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// Identify CPU ID
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bl ASM_PFX(ArmReadMpidr)
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// Keep a copy of the MpId register value
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mov x5, x0
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// Is it the Primary Core ?
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bl ASM_PFX(ArmPlatformIsPrimaryCore)
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// Get the top of the primary stacks (and the base of the secondary stacks)
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MOV64 (x1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))
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// x0 is equal to 1 if I am the primary core
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cmp x0, #1
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b.eq _SetupPrimaryCoreStack
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_SetupSecondaryCoreStack:
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// x1 contains the base of the secondary stacks
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// Get the Core Position
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mov x6, x1 // Save base of the secondary stacks
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mov x0, x5
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bl ASM_PFX(ArmPlatformGetCorePosition)
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// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
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add x0, x0, #1
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// StackOffset = CorePos * StackSize
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MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
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mul x0, x0, x2
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// SP = StackBase + StackOffset
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add sp, x6, x0
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_PrepareArguments:
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// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
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MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))
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ldr x1, [x2, #8]
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// Move sec startup address into a data register
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// Ensure we're jumping to FV version of the code (not boot remapped alias)
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ldr x3, =ASM_PFX(CEntryPoint)
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// Set the frame pointer to NULL so any backtraces terminate here
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mov x29, xzr
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// Jump to PrePeiCore C code
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// x0 = mp_id
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// x1 = pei_core_address
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mov x0, x5
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blr x3
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_SetupPrimaryCoreStack:
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mov sp, x1
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MOV64 (x8, FixedPcdGet64 (PcdCPUCoresStackBase))
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MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\
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FixedPcdGet32 (PcdInitValueInTempStack) << 32)
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0:stp x9, x9, [x8], #16
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cmp x8, x1
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b.lt 0b
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b _PrepareArguments
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