f4dfad05dd
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
90 lines
2.3 KiB
NASM
90 lines
2.3 KiB
NASM
//
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// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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#include <AutoGen.h>
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INCLUDE AsmMacroIoLib.inc
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IMPORT CEntryPoint
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IMPORT ArmPlatformGetCorePosition
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IMPORT ArmPlatformIsPrimaryCore
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IMPORT ArmReadMpidr
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IMPORT ArmPlatformPeiBootAction
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EXPORT _ModuleEntryPoint
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PRESERVE8
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AREA PrePeiCoreEntryPoint, CODE, READONLY
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StartupAddr DCD CEntryPoint
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_ModuleEntryPoint
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// Do early platform specific actions
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bl ArmPlatformPeiBootAction
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// Identify CPU ID
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bl ArmReadMpidr
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// Keep a copy of the MpId register value
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mov r5, r0
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// Is it the Primary Core ?
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bl ArmPlatformIsPrimaryCore
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// Get the top of the primary stacks (and the base of the secondary stacks)
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mov32 r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize)
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// r0 is equal to 1 if I am the primary core
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cmp r0, #1
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beq _SetupPrimaryCoreStack
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_SetupSecondaryCoreStack
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// r1 contains the base of the secondary stacks
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// Get the Core Position
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mov r6, r1 // Save base of the secondary stacks
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mov r0, r5
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bl ArmPlatformGetCorePosition
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// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
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add r0, r0, #1
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// StackOffset = CorePos * StackSize
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mov32 r2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)
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mul r0, r0, r2
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// SP = StackBase + StackOffset
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add sp, r6, r0
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_PrepareArguments
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// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
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mov32 r2, FixedPcdGet32(PcdFvBaseAddress)
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ldr r1, [r2, #4]
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// Move sec startup address into a data register
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// Ensure we're jumping to FV version of the code (not boot remapped alias)
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ldr r3, StartupAddr
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// Jump to PrePeiCore C code
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// r0 = mp_id
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// r1 = pei_core_address
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mov r0, r5
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blx r3
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_SetupPrimaryCoreStack
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mov sp, r1
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mov32 r8, FixedPcdGet64 (PcdCPUCoresStackBase)
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mov32 r9, FixedPcdGet32 (PcdInitValueInTempStack)
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mov r10, r9
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mov r11, r9
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mov r12, r9
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0:stm r8!, {r9-r12}
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cmp r8, r1
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blt 0b
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b _PrepareArguments
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_NeverReturn
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b _NeverReturn
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END
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