3fd8800954
implementation. Implement RISC-V CPU related functions in BaseCpuLib. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
20 lines
449 B
ArmAsm
20 lines
449 B
ArmAsm
//------------------------------------------------------------------------------
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//
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// CpuSleep for RISC-V
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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.data
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.align 3
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.section .text
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.global ASM_PFX(_CpuSleep)
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ASM_PFX(_CpuSleep):
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wfi
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ret
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