https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
		
			
				
	
	
		
			264 lines
		
	
	
		
			5.3 KiB
		
	
	
	
		
			ArmAsm
		
	
	
		
			Executable File
		
	
	
	
	
			
		
		
	
	
			264 lines
		
	
	
		
			5.3 KiB
		
	
	
	
		
			ArmAsm
		
	
	
		
			Executable File
		
	
	
	
	
| #------------------------------------------------------------------------------
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| #
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| # Replacement for Math64.c that is coded to use older GCC intrinsics.
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| # Doing this reduces the number of intrinsics that are required when
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| # you port to a new version of gcc.
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| #
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| # Need to split this into multple files to size optimize the image.
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| #
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| # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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| # SPDX-License-Identifier: BSD-2-Clause-Patent
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| #
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| #------------------------------------------------------------------------------
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| 
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|   .text
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathLShiftU64)
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| 
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| ASM_PFX(InternalMathLShiftU64):
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|   stmfd  sp!, {r4, r5, r6}
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|   mov  r6, r1
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|   rsb  ip, r2, #32
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|   mov  r4, r6, asl r2
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|   subs  r1, r2, #32
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|   orr  r4, r4, r0, lsr ip
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|   mov  r3, r0, asl r2
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|   movpl  r4, r0, asl r1
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|   mov  r5, r0
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|   mov  r0, r3
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|   mov  r1, r4
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|   ldmfd  sp!, {r4, r5, r6}
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|   bx  lr
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathRShiftU64)
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| 
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| ASM_PFX(InternalMathRShiftU64):
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|   stmfd  sp!, {r4, r5, r6}
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|   mov  r5, r0
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|   rsb  ip, r2, #32
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|   mov  r3, r5, lsr r2
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|   subs  r0, r2, #32
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|   orr  r3, r3, r1, asl ip
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|   mov  r4, r1, lsr r2
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|   movpl  r3, r1, lsr r0
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|   mov  r6, r1
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|   mov  r0, r3
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|   mov  r1, r4
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|   ldmfd  sp!, {r4, r5, r6}
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|   bx  lr
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathARShiftU64)
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| 
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| ASM_PFX(InternalMathARShiftU64):
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|   stmfd  sp!, {r4, r5, r6}
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|   mov  r5, r0
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|   rsb  ip, r2, #32
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|   mov  r3, r5, lsr r2
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|   subs  r0, r2, #32
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|   orr  r3, r3, r1, asl ip
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|   mov  r4, r1, asr r2
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|   movpl  r3, r1, asr r0
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|   mov  r6, r1
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|   mov  r0, r3
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|   mov  r1, r4
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|   ldmfd  sp!, {r4, r5, r6}
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|   bx  lr
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathLRotU64)
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| 
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| ASM_PFX(InternalMathLRotU64):
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|   stmfd  sp!, {r4, r5, r6, r7, lr}
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|   add  r7, sp, #12
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|   mov  r6, r1
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|   rsb  ip, r2, #32
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|   mov  r4, r6, asl r2
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|   rsb  lr, r2, #64
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|   subs  r1, r2, #32
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|   orr  r4, r4, r0, lsr ip
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|   mov  r3, r0, asl r2
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|   movpl  r4, r0, asl r1
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|   sub  ip, r2, #32
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|   mov  r5, r0
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|   mov  r0, r0, lsr lr
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|   rsbs  r2, r2, #32
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|   orr  r0, r0, r6, asl ip
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|   mov  r1, r6, lsr lr
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|   movpl  r0, r6, lsr r2
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|   orr  r1, r1, r4
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|   orr  r0, r0, r3
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|   ldmfd  sp!, {r4, r5, r6, r7, pc}
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| 
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathRRotU64)
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| 
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| ASM_PFX(InternalMathRRotU64):
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|   stmfd  sp!, {r4, r5, r6, r7, lr}
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|   add  r7, sp, #12
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|   mov  r5, r0
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|   rsb  ip, r2, #32
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|   mov  r3, r5, lsr r2
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|   rsb  lr, r2, #64
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|   subs  r0, r2, #32
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|   orr  r3, r3, r1, asl ip
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|   mov  r4, r1, lsr r2
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|   movpl  r3, r1, lsr r0
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|   sub  ip, r2, #32
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|   mov  r6, r1
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|   mov  r1, r1, asl lr
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|   rsbs  r2, r2, #32
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|   orr  r1, r1, r5, lsr ip
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|   mov  r0, r5, asl lr
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|   movpl  r1, r5, asl r2
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|   orr  r0, r0, r3
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|   orr  r1, r1, r4
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|   ldmfd  sp!, {r4, r5, r6, r7, pc}
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathMultU64x32)
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| 
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| ASM_PFX(InternalMathMultU64x32):
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|   stmfd  sp!, {r7, lr}
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|   add  r7, sp, #0
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|   mov  r3, #0
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|   mov  ip, r0
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|   mov  lr, r1
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|   umull  r0, r1, ip, r2
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|   mla  r1, lr, r2, r1
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|   mla  r1, ip, r3, r1
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|   ldmfd  sp!, {r7, pc}
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathMultU64x64)
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| 
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| ASM_PFX(InternalMathMultU64x64):
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|   stmfd  sp!, {r7, lr}
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|   add  r7, sp, #0
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|   mov  ip, r0
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|   mov  lr, r1
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|   umull  r0, r1, ip, r2
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|   mla  r1, lr, r2, r1
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|   mla  r1, ip, r3, r1
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|   ldmfd  sp!, {r7, pc}
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathDivU64x32)
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| 
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| ASM_PFX(InternalMathDivU64x32):
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|   stmfd  sp!, {r7, lr}
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|   add  r7, sp, #0
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|   mov  r3, #0
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|   bl   ASM_PFX(__udivdi3)
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|   ldmfd  sp!, {r7, pc}
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| 
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathModU64x32)
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| 
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| ASM_PFX(InternalMathModU64x32):
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|   stmfd  sp!, {r7, lr}
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|   add  r7, sp, #0
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|   mov  r3, #0
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|   bl   ASM_PFX(__umoddi3)
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|   ldmfd  sp!, {r7, pc}
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| 
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathDivRemU64x32)
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| 
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| ASM_PFX(InternalMathDivRemU64x32):
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|   stmfd  sp!, {r4, r5, r6, r7, lr}
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|   add  r7, sp, #12
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|   stmfd  sp!, {r10, r11}
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|   subs  r6, r3, #0
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|   mov  r10, r0
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|   mov  r11, r1
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|   moveq  r4, r2
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|   moveq  r5, #0
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|   beq  L22
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|   mov  r4, r2
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|   mov  r5, #0
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|   mov  r3, #0
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|   bl   ASM_PFX(__umoddi3)
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|   str  r0, [r6, #0]
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| L22:
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|   mov  r0, r10
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|   mov  r1, r11
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|   mov  r2, r4
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|   mov  r3, r5
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|   bl   ASM_PFX(__udivdi3)
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|   ldmfd  sp!, {r10, r11}
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|   ldmfd  sp!, {r4, r5, r6, r7, pc}
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| 
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathDivRemU64x64)
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| 
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| ASM_PFX(InternalMathDivRemU64x64):
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|   stmfd  sp!, {r4, r5, r6, r7, lr}
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|   add  r7, sp, #12
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|   stmfd  sp!, {r10, r11}
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|   ldr  r6, [sp, #28]
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|   mov  r4, r0
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|   cmp  r6, #0
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|   mov  r5, r1
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|   mov  r10, r2
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|   mov  r11, r3
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|   beq  L26
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|   bl   ASM_PFX(__umoddi3)
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|   stmia  r6, {r0-r1}
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| L26:
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|   mov  r0, r4
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|   mov  r1, r5
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|   mov  r2, r10
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|   mov  r3, r11
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|   bl   ASM_PFX(__udivdi3)
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|   ldmfd  sp!, {r10, r11}
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|   ldmfd  sp!, {r4, r5, r6, r7, pc}
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| 
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathDivRemS64x64)
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| 
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| ASM_PFX(InternalMathDivRemS64x64):
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|   stmfd  sp!, {r4, r5, r6, r7, lr}
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|   add  r7, sp, #12
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|   stmfd  sp!, {r10, r11}
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|   ldr  r6, [sp, #28]
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|   mov  r4, r0
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|   cmp  r6, #0
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|   mov  r5, r1
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|   mov  r10, r2
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|   mov  r11, r3
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|   beq  L30
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|   bl   ASM_PFX(__moddi3)
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|   stmia  r6, {r0-r1}
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| L30:
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|   mov  r0, r4
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|   mov  r1, r5
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|   mov  r2, r10
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|   mov  r3, r11
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|   bl   ASM_PFX(__divdi3)
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|   ldmfd  sp!, {r10, r11}
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|   ldmfd  sp!, {r4, r5, r6, r7, pc}
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| 
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| 
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|   .align 2
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|   GCC_ASM_EXPORT(InternalMathSwapBytes64)
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| 
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| ASM_PFX(InternalMathSwapBytes64):
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|   stmfd  sp!, {r4, r5, r7, lr}
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|   mov  r5, r1
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|   bl  ASM_PFX(SwapBytes32)
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|   mov  r4, r0
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|   mov  r0, r5
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|   bl  ASM_PFX(SwapBytes32)
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|   mov  r1, r4
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|   ldmfd  sp!, {r4, r5, r7, pc}
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| 
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| 
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| ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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