4ac0296201
*v2: refine the coding format.
https://bugzilla.tianocore.org/show_bug.cgi?id=3284
This patch is to support XSETBV instruction so as to support
Extended Control Register(XCR) write.
Extended Control Register(XCR) read has already been supported
by below commit to support XGETBV instruction:
9b3ca509ab
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ni Ray <ray.ni@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
35 lines
891 B
NASM
35 lines
891 B
NASM
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; XSetBv.nasm
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;
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; Abstract:
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;
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; AsmXSetBv function
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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DEFAULT REL
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SECTION .text
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;------------------------------------------------------------------------------
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; UINT64
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; EFIAPI
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; AsmXSetBv (
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; IN UINT32 Index,
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; IN UINT64 Value
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(AsmXSetBv)
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ASM_PFX(AsmXSetBv):
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mov rax, rdx ; meanwhile, rax <- return value
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shr rdx, 0x20 ; edx:eax contains the value to write
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xsetbv
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ret
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