e5efcf8be8
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiPayloadPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
/** @file
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x64-specifc functionality for DxeLoad.
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Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/HobLib.h>
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#include "X64/VirtualMemory.h"
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#include "UefiPayloadEntry.h"
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#define STACK_SIZE 0x20000
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/**
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Transfers control to DxeCore.
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This function performs a CPU architecture specific operations to execute
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the entry point of DxeCore with the parameters of HobList.
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It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
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@param DxeCoreEntryPoint The entry point of DxeCore.
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@param HobList The start of HobList passed to DxeCore.
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**/
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VOID
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HandOffToDxeCore (
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IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
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IN EFI_PEI_HOB_POINTERS HobList
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)
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{
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VOID *BaseOfStack;
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VOID *TopOfStack;
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UINTN PageTables;
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VOID *GhcbBase;
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UINTN GhcbSize;
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//
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// Clear page 0 and mark it as allocated if NULL pointer detection is enabled.
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//
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if (IsNullDetectionEnabled ()) {
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ClearFirst4KPage (HobList.Raw);
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BuildMemoryAllocationHob (0, EFI_PAGES_TO_SIZE (1), EfiBootServicesData);
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}
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//
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// Allocate 128KB for the Stack
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//
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BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
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ASSERT (BaseOfStack != NULL);
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//
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// Compute the top of the stack we were allocated. Pre-allocate a UINTN
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// for safety.
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//
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TopOfStack = (VOID *)((UINTN)BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
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TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
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//
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// Get the address and size of the GHCB pages
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//
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GhcbBase = 0;
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GhcbSize = 0;
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PageTables = 0;
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if (FeaturePcdGet (PcdDxeIplBuildPageTables)) {
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//
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// Create page table and save PageMapLevel4 to CR3
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//
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PageTables = CreateIdentityMappingPageTables (
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(EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack,
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STACK_SIZE,
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(EFI_PHYSICAL_ADDRESS)(UINTN)GhcbBase,
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GhcbSize
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);
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} else {
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//
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// Set NX for stack feature also require PcdDxeIplBuildPageTables be TRUE
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// for the DxeIpl and the DxeCore are both X64.
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//
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ASSERT (PcdGetBool (PcdSetNxForStack) == FALSE);
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ASSERT (PcdGetBool (PcdCpuStackGuard) == FALSE);
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}
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if (FeaturePcdGet (PcdDxeIplBuildPageTables)) {
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AsmWriteCr3 (PageTables);
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}
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//
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// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
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//
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UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack, STACK_SIZE);
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//
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// Transfer the control to the entry point of DxeCore.
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//
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SwitchStack (
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(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
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HobList.Raw,
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NULL,
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TopOfStack
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);
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}
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